MIL-M-38510-291 Microcircuits, Digital, Cmos 16,384 Bit Static Random Access Memory Ram Monolithic SiliconThis specification covers the detail requirements for monolithic silicon, CMOS, 16,384 bit static random access memory microcircuits. Two product assurance classes and a choice of case outlines, lead finishes, and radiation hardness assured RHA products are reflected in the complete part number. For this product, the requirements of MIL-M-38510 have been superseded by MIL-PRF-38535, see 6.4.

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MIL-M-38510/291B

APPENDIX A

A.3.3  Algorithm C (pattern 3).

A.3.3.1  March data, data background = all "0's".

This pattern tests for address uniqueness and multiple selection.  It is performed in the following manner:

Step 1.  Load memory with background data. Step 2.  Read location 0.

Step 3.  Write data complement in location 0. Step 4.  Read data complement in location 0.

Step 5.  Repeat steps 2 through 4 for all other locations in memory (sequentially). Step 6.  Read data complement at location 0.

Step 7.  Write data at location 0. Step 8.  Read data at location 0.

Step 9.  Repeat steps 6 through 8 for all other locations in the memory (sequentially). Step 10.  Repeat steps 1 through 9 with data background of all "1's".

A.3.4  Algorithm D (pattern 4).

A.3.4.1  Data retention, data background = checkerboard.

This algorithm tests for data retention mode functionality.  It is performed in the following manner: Step 1.  Load memory with background data.

Step 2.  Set chip enable = VCC.

Step 3.  Reduce VCC  and chip enable to minimum VDR.

Step 4.  Pause for 200 ms.

Step 5.  Bring VCC  and chip enable back up and test for background data. Step 6.  Repeat steps 1 through 5 with complemented background data.

A.3.5  Algorithm E (pattern 5).

A.3.5.1  Checkerboard,  checkerboard.

Step 1.  Load memory with a checkerboard pattern.

Step 2.  Read the memory, verifying the checkerboard pattern. Step 3.  Load the memory with a checkerboard pattern.

Step 4.  Read the memory, verifying the checkerboard pattern.

A.3.6  Algorithm F (pattern 6). A.3.6.1  Butterfly.

Step 1.  Write a background pattern of "0's" throughout the memory. Step 2.  Write a "1" (test bit) at the first location.

Step 3.  Read the test cell and the next sequential cell in the same row, then the test cell and the next sequential cell in the same column, until all cells have been tested in the same row and column as the test cell.

Step 4.  Rewrite the test cell to "0", write a "1" into the next cell which will become the test cell, then repeat the ping-pong row column march.

Step 5.  After all cells have been used as test cells, repeat the test with complement data.

A.3.7  Algorithm G (pattern 7). A.3.7.1  Spiral complement.

Step 1.  Write a background pattern of "0's" in all cells.

Step 2.  Beginning at cell "0", write and read a diagonal of "1's" on the field "0's".

Step 3.  Shift the diagonal one increment in the x direction until each row has been used as a starting point of the diagonal and all cells within the diagonal have been tested.

Step 4.  Repeat the test with complement data.

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