MIL-M-38510/291B
TABLE I. Electrical performance characteristics (device types 07 and 08).
Test |
Symbol |
Conditions VSS = 0 V, VCC = 5.5 V -55°C ≤ TC ≤ +125°C unless otherwise specified |
Device types |
Limits |
Unit |
|
Min |
Max |
|||||
Low level output voltage |
VOL |
VCC = 4.5 V; IOL = 5.0 mA |
07 08 |
0.4 0.4 |
V |
|
High level output voltage |
VOH |
VCC = 4.5 V; IOH = -5.0 mA |
07 08 |
4.0 4.0 |
V |
|
Input leakage current |
IIH |
VCC = 5.5 V; VIN = 5.5 V |
07 08 |
1.0 1.0 |
µA |
|
Input leakage current |
IIL |
VCC = 5.5 V; VIN = GND |
07 08 |
-1.0 -1.0 |
µA |
|
High impedance output leakage |
IOHZ |
VCC = 5.5 V |
07 08 |
10.0 10.0 |
µA |
|
High impedance |
IOLZ |
VCC = 5.5 V |
07 08 |
-10.0 -10.0 |
µA |
|
Standby supply |
ICC |
VCC = 5.5 V |
07 08 |
200 5 |
µA mA |
|
Data retention supply voltage |
VCCDR |
VCC = 3.0 V minimum (see power down test in table III) |
07 08 |
3.0 3.0 |
V |
|
Operating current |
ICCOP |
TC = +25°C, VCC = 5.5 V f = 1 MHz |
07 08 |
6 6 |
mA |
|
Data retention quiescent supply current |
ICCDR |
VCC = 3.0 V; I0 = 0; VI = VCC or GND |
07 08 |
100 100 |
µA |
|
Input capacitance |
CI |
VCC = 5.5 V; VIN = VCC or GND f = 1 MHz |
07 08 |
8 8 |
pF |
|
Address access time |
tAVQV |
See table III |
07 08 |
150 175 |
ns |
|
Chip enable access |
tELQV |
07 08 |
150 175 |
ns |
||
Read cycle time |
tAVAV |
07 08 |
150 175 |
ns |
||
Chip enable output time |
tELQX |
07 08 |
20 40 |
ns |
See footnotes at end of table.
8
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