MIL-M-38510/291B
TABLE I. Electrical performance characteristics (device types 07 and 08) - Continued.
Test |
Symbol |
Conditions VSS = 0 V, VCC = 5.5 V -55°C ≤ TC ≤ +125°C unless otherwise specified |
Device types |
Limits |
Unit |
|
Min |
Max |
|||||
Chip enable output disable |
tEHQZ 1/ |
See table III |
07 08 |
25 50 |
ns |
|
Chip enable pulse negative width |
tELEH |
07 08 |
100 125 |
ns |
||
Chip disable output hold time |
tEHQX 1/ |
07 08 |
20 40 |
ns |
||
Address setup time |
tAVEL |
07 08 |
0 0 |
ns |
||
Address invalid output hold time |
tAXQX 1/ |
07 08 |
40 60 |
ns |
||
Write enable pulse width |
tWLWH |
07 08 |
75 100 |
ns |
||
Write enable pulse setup time |
tWLEH |
07 08 |
100 125 |
ns |
||
Address setup time |
tAVWL |
07 08 |
10 10 |
ns |
||
Chip enable to end-of-write |
tELWH |
See table III I0 = 0; VI = VCC or GND |
07 08 |
100 125 |
ns |
|
Write disable output enable time |
tWHQX 1/ |
See table III |
07 08 |
0 0 |
ns |
|
Address valid to end-of-write |
tAVWH |
07 08 |
100 125 |
ns |
||
Address hold time |
tWHAX |
07 08 |
20 25 |
ns |
||
Address hold time |
tEHAX |
07 08 |
0 0 |
ns |
||
Address valid to end-of-write |
tAVEH |
07 08 |
100 125 |
ns |
||
Write enable output disable time |
tWLQZ 1/ |
07 08 |
25 50 |
ns |
||
Data setup time |
tDVWH |
07 08 |
75 100 |
ns |
||
Data hold time |
tWHDX |
07 08 |
20 20 |
ns |
||
Data setup time |
tDVEH |
07 08 |
75 100 |
ns |
||
Data hold time |
tEHDX |
07 08 |
0 0 |
ns |
1/ This parameter is guaranteed but not tested.
9
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