MIL-M-38510-291 Microcircuits, Digital, Cmos 16,384 Bit Static Random Access Memory Ram Monolithic SiliconThis specification covers the detail requirements for monolithic silicon, CMOS, 16,384 bit static random access memory microcircuits. Two product assurance classes and a choice of case outlines, lead finishes, and radiation hardness assured RHA products are reflected in the complete part number. For this product, the requirements of MIL-M-38510 have been superseded by MIL-PRF-38535, see 6.4.

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MIL-M-38510/291B

6.5  Abbreviations, symbols and definitions.   The abbreviations, symbols, and definitions used herein are defined in MIL-PRF-38535 and MIL-HDBK-1331, and as follows:

VSS .....................................................Common or reference voltage mode. VCC.....................................................Supply voltage.

A0 - A13   ..........................................Address inputs, used to address 1 of 16, 384/1 bit locations in static

storage array.

CE ....................................................Chip enable, used along with the write enable ( WE ) signal to control the states of the data in (DIN) and data out (DOUT  / DQ) buses.

DOUT / DQ............................................Data output.

DIN .....................................................Data input through which data is stored.

WE ...................................................Write enable, used to select the Read or Write mode. ICC ......................................................Supply current.

IIH, IIL ..................................................Input leakage current.

IOHZ, IOLZ.............................................High impedance output leakage current.

VIL ......................................................Logical low input voltage.

VIH......................................................Logical high input voltage.

VOL .....................................................Logical low output voltage.

VOH ....................................................Logical high output voltage.

Ci .......................................................Input capacitance.

Co.......................................................Output capacitance.

tELQV ...................................................Chip enable access time.

tAVQV...................................................Address access time.

tEHQZ...................................................Chip enable to output disable.

tAVAV ...................................................Read cycle time.

tAVQX...................................................Output hold after address change.

tELQX ...................................................Chip enable to output active.

tWLWH ..................................................Write pulse width.

tELWH...................................................Chip enable to end of write.

tDVWH ..................................................Data setup to end of write.

tWHDX ..................................................Data hold after end of write.

tAVWL...................................................Address setup before write enable low.

tAVWH ..................................................Address setup up to end of write.

tWHAV ..................................................Write recovery time

tOLQV...................................................Output enable access time.

tOLQX...................................................Output enable to output active.

tOHQX ..................................................Output enable to output disable time.

tAVEL ...................................................Address to chip enable setup time.

tELAX ...................................................Address to chip enable hold time.

tELEH ...................................................Chip enable pulse negative width.

tEHEL ...................................................Chip enable pulse positive width.

tWLEH...................................................Write enable pulse setup time.

tELEL....................................................Read or write cycle time.

6.5.1  Timing parameter abbreviations.  All timing abbreviations used lower case characters with upper case character subscripts.  The initial character is always t and is followed by four descriptors.  These characters specify two signal points arranged in a "from-to" sequence that define a timing interval.  The two descriptors for each signal point specify the signal name and the signal transition.  Thus, the format is:

Signal name to which interval is defined ----------------------------│         │

Transition direction for second signal ------------------------------------│

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