MIL-M-38510-291 Microcircuits, Digital, Cmos 16,384 Bit Static Random Access Memory Ram Monolithic SiliconThis specification covers the detail requirements for monolithic silicon, CMOS, 16,384 bit static random access memory microcircuits. Two product assurance classes and a choice of case outlines, lead finishes, and radiation hardness assured RHA products are reflected in the complete part number. For this product, the requirements of MIL-M-38510 have been superseded by MIL-PRF-38535, see 6.4.

Pages 1 - 2 - 3 - 4 - 5 - 6 - 7 - 8 - 9 - 10 - 11 - 12 - 13 - 14 - 15 - 16 - 17 - 18 - 19 - 20 - 21 - 22 - 23 - 24 - 25 - 26 - 27 - 28 - 29 - 30 - 31 - 32 - 33 - 34 - 35 - 36 - 37 - 38 - 39 - 40 - 41 - 42 - 43 - 44 - 45 - 46 - 47 - 48 - 49 - 50 - 51 - 52 - 53 - 54 - 55 - 56 - 57 - 58 - 59 - 60 - 61 - 62 - 63 - 64 - 65

MIL-M-385101291B

11    Pins not designated may be "high" level logic, or "low" level logic.  Exceptions are the input1output terminals, in the output condition, may be open.

21    All input levels and timing edges are set to table I limits with read cycle timing:  For device type 02, outputs are open.  I0 = 0 mA.

Device type 02 inputs = GND and VCC.

31    Outputs loaded with load as specified on figure 5.

41    An input preconditioning logic sequence shall be applied that results in a logic "0" at the output to be measured.  Logic input levels and forcing current during measurement shall be VIL  = 0.8 V, IOL  = 3.2 mA.

51    An input preconditioning logic sequence shall be applied that results in a logic "1" at the output to be measured.  Logic input levels and forcing current during measurement shall be VIH  = 2.4 V, IOH = -1.0 mA.

61    See 4.4.1c.

71    Tested as follows:  f = 2 MHz, VIL = 0.4 V, VIH  = 2.4 V, IOL = -4 mA, IOH = +4.0 µA, VOH  � 1.5 V and VOL  ≤ 1.5 V.

81    Test is done with addresses held stable, VCC  = 2.0 V, and all other inputs held at VCC.  The data retention test condition shall be held for 250 milliseconds before measurements.  The data must remain valid after power is returned to device.

91    Timing waveforms shown on figure 4 shall be applied while performing a WRITE1WRITE address complement pattern

(see figure 8).  Device type 02 uses patterns 1, 3, 5 (see Appendix A).  A combination of test patterns is used to verify all of the ac parameters.  Each pattern does not test all ac parameters inclusive.  This procedure ensures that the following parameters meet

the specified limits:

The output shall be loaded with the load specified on figure 5.  If the test equipment limitations prevent the simultaneous application or verification of all the specified parameters, multiple executions of the algorithm may be required to effect the measurement of all dynamic parameters.

16