MIL-M-38510-291 Microcircuits, Digital, Cmos 16,384 Bit Static Random Access Memory Ram Monolithic SiliconThis specification covers the detail requirements for monolithic silicon, CMOS, 16,384 bit static random access memory microcircuits. Two product assurance classes and a choice of case outlines, lead finishes, and radiation hardness assured RHA products are reflected in the complete part number. For this product, the requirements of MIL-M-38510 have been superseded by MIL-PRF-38535, see 6.4.

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MIL-M-38510/291B

1/    Pins not designated may be "high" level logic, or "low" level logic.  Exceptions are the input/output terminals, in the output condition, may be open.

2/    All inputs levels and timing edges are set to table I limits with read cycle timing; VIL  = 0.4 V and VIH  = 2.2 V for device types 01 and 05.

3/    Outputs loaded with load as specified on figure 5.

4/    Test is done with addresses held stable, and all inputs held at VIL = 0.4 V and VIH  = 2.2 V for device types 01 and 05.

5/    Test is done with addresses held stable, and all inputs held at VIL = 0.4 V and VIH  = VCC   -0.3 V.

6/    Test is done with addresses held stable, VCC  = 2.0 V, and all other inputs held at VCC.  The data retention test condition shall be held for 250 milliseconds before measurements. The data must remain valid after power is returned to device.

7/    For VOL  or VOH, testing all terminals, only the worst case variables data shall be recorded, and variables data for each failed terminal.  Attributes data otherwise.

8/    An input preconditioning logic sequence shall be applied that results in a logic "0" at the output to be measured.  Logic input levels and forcing current during measurement shall be VIL  = 0.8 V, IOL = 2.0 mA.

9/    An input preconditioning logic sequence shall be applied that results in a logic "1" at the output to be measured.  Logic input levels and forcing current during measurement shall be VIH  = 2.2 V, IOH  = -1.0 mA.

10/  See 4.4.1c.

11/  Since the object of the NOT WRITE pattern (see figure 7) is to verify that the device may not be written into when it is disabled, the waveforms shown on figure 4   may be applied using nominal timing.  The outputs shall be loaded with the load specified on figure 5.

12/  Timing waveforms shown on figure 4  shall be applied while performing a WRITE/WRITE address complement pattern (see figure 8).  This procedure ensures that the following parameters meet the specified limits:

The output shall be loaded with the load specified on figure 5.  If the test equipment limitations prevent the simultaneous application or verification of all the specified parameters, multiple executions of the algorithm may be required to effect the measurement of all dynamic parameters.

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