MIL-M-38510-291 Microcircuits, Digital, Cmos 16,384 Bit Static Random Access Memory Ram Monolithic SiliconThis specification covers the detail requirements for monolithic silicon, CMOS, 16,384 bit static random access memory microcircuits. Two product assurance classes and a choice of case outlines, lead finishes, and radiation hardness assured RHA products are reflected in the complete part number. For this product, the requirements of MIL-M-38510 have been superseded by MIL-PRF-38535, see 6.4.

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MIL-M-38510/291B APPENDIX A

FUNCTIONAL ALGORITHMS

A.1  SCOPE

A.1.1  Scope.  Functional algorithms are test patterns which define the exact sequence of the events used to verify proper operation of a random access memory (RAM).  Each algorithm serves a specific purpose for the testing of the device.  It is understood that all manufacturers do not have the same test equipment; therefore, it becomes the responsibility of each manufacturer to guarantee that the test patterns described herein are followed as closely as possible, or equivalent patterns be used that serve the same purpose.  Each manufacturer should demonstrate that this condition will be met.  Algorithms shall be applied to the device in a topologically pure fashion.  This Appendix is a mandatory part of the specification.  The information contained herein is intended for compliance.

A.2  APPLICABLE DOCUMENTS.  This section is not applicable to this appendix. A.3  ALGORITHMS.

A.3.1  Algorithm A (pattern 1).

A.3.1.1  Address complement, data background = all "0's".

This pattern produces maximum address line noise.  It is performed in the following manner: Step 1.  Load memory with background data.

Step 2.  Read minimum address location.

Step 3.  Load minimum address location with "1". Step 4.  Read maximum address location.

Step 5.  Load maximum address location with "1".

Step 6.  Read minimum address location +1.

Step 7.  Load minimum address location +1 with "1". Step 8.  Read maximum address location -1.

Step 9.  Load maximum address location -1 with "1".

Step 10.  Repeat steps 2 through 9 until all address locations have been read and loaded with "1's". Step 11.  Repeat steps 2 through 10 reading "1's" and loading "0's".

Step 12.  Read memory, all "0's".

A.3.2  Algorithm B (pattern 2).

A.3.2.1  GALPAT (ping pong) data background = "0".

This pattern tests for performance sensitivities by testing all possible combinations of address and data out transitions.  It is performed in the following manner:

Step 1.  Load memory with data background.

Step 2.  Write data complement in location 0 (test bit).

Step 3.  Alternately read test bit and each location in the array. Step 4.  Write the test bit back to background data.

Step 5.  Repeat steps 2 through 4 with each location in the array.

Step 6.  Repeat steps 1 through 5 with complemented background data.

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