MIL-M-38510-291 Microcircuits, Digital, Cmos 16,384 Bit Static Random Access Memory Ram Monolithic SiliconThis specification covers the detail requirements for monolithic silicon, CMOS, 16,384 bit static random access memory microcircuits. Two product assurance classes and a choice of case outlines, lead finishes, and radiation hardness assured RHA products are reflected in the complete part number. For this product, the requirements of MIL-M-38510 have been superseded by MIL-PRF-38535, see 6.4.

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MIL-M-38510I291B

11I    Power down test (PWRDWN) terminal conditions shall be as follows:

a.    Use timing parameters and limits specified on figure 4. b.    VOL  < VCC I 2; VOH  > VCC I 2.

c.    Use load specified on figure 5.

d.    VIL  = 0 V; VIH = 4.5 V.

e.        The power down test shall be performed as follows: (1)   Power up RAM to VCC  = 4.5 V.

(2)   Write topologically true checkerboard pattern into RAM memory array (see Appendix A).

(3)   Reduce VCC  to 3.0 V.  All device inputs shall be reduced along with VCC  exercising special care to avoid latch-up. (4)   Maintain RAM at reduced voltage for 500 ms (0.5 second) minimum.

(5)   Raise VCC  to 4.5 V.

(6)   Verify RAM contents to be unchanged from pattern written in (2) above.

(7)   Repeat steps (1) through (6), except use the complement of the first checkerboard pattern.

12I  Functional test terminal conditions shall be as follows:

a.    Use timing parameter and limits specified on figure 4.

b.    The output voltages shall be:  VOL  < VCC I 2; VOH  > VCC I 2. c.    Use CK,  CK , butterfly, spiral complement patterns.

d.    Use load specified on figure 5.

e.    VCC  = 4.5 V; VIL  = 0.8 V; VIH = VCC   -  1.5 V.

13I  Timing test terminal conditions shall be as follows:

a.    Use timing parameter and limits specified on figure 4. b.    VOL  < VCC I 2;   VOH  > VCC I 2

c.    Use CK,  CK , patterns.

d.    Use load specified on figure 5.

e.    VCC  = 4.5 V; VIL  = 0.8 V; VIH = VCC   -  1.5 V.

14I  Operating current test (ICCOP) terminal conditions shall be as follows:

a.    Use timing parameters and limits specified on figure 4.

b.    Use topologically true checkerboard pattern (see Appendix A). c.    Use load specified on figure 5.

d.    VIL  = 0 V; VIH = 5.5 V.

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