MIL-M-38510-291 Microcircuits, Digital, Cmos 16,384 Bit Static Random Access Memory Ram Monolithic SiliconThis specification covers the detail requirements for monolithic silicon, CMOS, 16,384 bit static random access memory microcircuits. Two product assurance classes and a choice of case outlines, lead finishes, and radiation hardness assured RHA products are reflected in the complete part number. For this product, the requirements of MIL-M-38510 have been superseded by MIL-PRF-38535, see 6.4.

Pages 1 - 2 - 3 - 4 - 5 - 6 - 7 - 8 - 9 - 10 - 11 - 12 - 13 - 14 - 15 - 16 - 17 - 18 - 19 - 20 - 21 - 22 - 23 - 24 - 25 - 26 - 27 - 28 - 29 - 30 - 31 - 32 - 33 - 34 - 35 - 36 - 37 - 38 - 39 - 40 - 41 - 42 - 43 - 44 - 45 - 46 - 47 - 48 - 49 - 50 - 51 - 52 - 53 - 54 - 55 - 56 - 57 - 58 - 59 - 60 - 61 - 62 - 63 - 64 - 65

MIL-M-38510/291B

TABLE VI. Group E end-point electrical parameter limits for devices 07 and 08.

Test	Symbol	Conditions 1/ VSS = 0 V, VCC = 5.5 V -55°C s TC s +125°C Unless otherwise specified	Device type	Limits		Unit
Test	Symbol		Device type	Min	Max	Unit
Low level output voltage	VOL	VCC = 4.5 V IOL = 5.0 mA	07 08		0.4 0.4	V V
High level output voltage	VOH	VCC = 4.5 V IOH = -5 mA	07 08	4.0 4.0		V V
Input leakage current	IIH	VCC = 5.5 V VIN = 5.5 V	07 08		1.0 1.0	µA µA
Input leakage current	IIL	VCC = 5.5 V VIN = GND	07 08		-1.0 -1.0	µA µA
High impedance output leakage	IOHZ	VCC = 5.5 V	07 08		10.0 10.0	µA µA
High impedance	IOLZ	VCC = 5.5 V	07 08		-10.0 -10.0	µA µA
Standby supply	ICC	VCC = 5.5 V	07 08		200 5	µA mA
Data retention supply voltage	VCCDR	VCC = 3.0 V minimum (see power down test in table III)	07 08	3.0 3.0		V V
Operating current	ICCOP	TC = +25°C, VCC = 5.5 V f = 1 MHz	07 08		6 6	mA mA
Data retention quiescent supply current	ICCDR	VCC = 3.0 V, IO = 0 VI = VCC or GND	07 08		100 100	µA µA
Input capacitance	Ci	VCC = 5.5 V, VIN = VCC or GND f = 1MHz	07 08		8 8	pF pF
Address access time	tAVQV	See table III	07 08	150 175		ns ns
Chip enable access	tELQV		07 08	150 175		ns ns
Read cycle time	tAVAV		07 08	150 175		ns ns
Chip enable output time	tELQX		07 08	20 40		ns ns
Chip enable output disable	tEHQZ 1/		07 08		25 50	ns ns
Chip enable pulse negative width	tELEH		07 08	100 125		ns ns
Chip disable output hold time	tEHQX		07 08	20 40		ns ns
Address setup time	tAVEL		07 08	0 0		ns ns
Address invalid output hold time	tAXQX		07 08	40 60		ns ns
Write enable pulse width	tWLWH		07 08	75 100		ns ns
Write enable pulse setup time	tWLEH		07 08	100 125		ns ns
Address setup time	tAVWL		07 08	0 0		ns ns
Chip enable to end of write	tELWH	See table III IO = 0, VI = VCC or GND	07 08	100 125		ns ns

See footnote at end of table.