MIL-M-38510-291 Microcircuits, Digital, Cmos 16,384 Bit Static Random Access Memory Ram Monolithic SiliconThis specification covers the detail requirements for monolithic silicon, CMOS, 16,384 bit static random access memory microcircuits. Two product assurance classes and a choice of case outlines, lead finishes, and radiation hardness assured RHA products are reflected in the complete part number. For this product, the requirements of MIL-M-38510 have been superseded by MIL-PRF-38535, see 6.4.

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TABLE III. Group A inspection for device types 03 and 09 - Continued. 11

Subgroup	Symbol	MIL- STD-883 method	Cases R,Y	1	2	3	4	5	6	7	8	9	10	11	12	13	14	15	16	17	18	19	20	Algorithm	Measured terminal	Test limits		Unit
Subgroup	Symbol	MIL- STD-883 method	Test no.	A0	A1	A2	A3	A4	A5	A6	DQ	WE	VSS	CE	DIN	A7	A8	A9	A10	A11	A12	A13	VCC	Algorithm	Measured terminal	Min	Max	Unit
4 TC=+25°C	CIN COUT	3012	43 44	61	61	61	61	61	61	61	61	61	GND "	61	61	61	61	61	61	61	61	61	61		Input Output		10 12	pF pF
7 TC=+25°C	I1O VDR	Function tests	45 46	71 81	71 81	71 81	71 81	71 81	71 81	71 81	71 81	71 81	" "	71 81	71 81	71 81	71 81	71 81	71 81	71 81	71 81	71 81	5.5 V 2.0 V	Pattern 5 Pattern 4
8	Same tests, terminal conditions, and limits as for subgroup 7, except TC = +125°C and -55°C.
9 TC=+25°C	Func- tional tests		47 48	91 91	91 91	91 91	91 91	91 91	91 91	91 91	91 91	91 91	GND "	91 91	91 91	91 91	91 91	91 91	91 91	91 91	91 91	91 91	4.5 V 5.5 V	Patterns 1,3,5 Patterns 1,3,5	DQ DQ
9 TC=+25°C	tELQV tELQV tAVQV tAVQV		49 50 51 52										" " " "										4.5 V 5.5 V 4.5 V 5.5 V	Pattern 3 Pattern 3 Pattern 3 Pattern 3	DQ DQ DQ DQ		85 " " "	ns " " "
10	Same tests, terminal conditions, and limits as for subgroup 9, except TC = +125°C.
11	Same tests, terminal conditions, and limits as for subgroup 9, except TC = -55°C.

11 Pins not designated may be "high" level logic, or "low" level logic. Exceptions are the input1output terminals, in the output condition, may be open.

21 All input levels and timing edges are set to table I limits with read cycle timing: Inputs = GND and VCC, outputs = open, IO = 0 mA.

31 Outputs loaded with load as specified on figure 5.

41 An input preconditioning logic sequence shall be applied that results in a logic "0" at the output to be measured. Logic input levels and forcing current during measurement shall be: VIL = 0.8 V, IOL = 8.0 mA.

51 An input preconditioning logic sequence shall be applied that results in a logic "1" at the output to be measured. Logic input levels and forcing current during measurement shall be: VIH = 2.2 V, IOH = -4.0 mA.

61 See 4.4.1c.

71 Tested as follows: f = 2 MHz, VIL = 0.4 V, VIH = 2.2 V, IOL = -4 mA, IOH = +4.0 µA, VOH � 1.5 V and VOL ≤ 1.5 V.

81 Test is done with addresses held stable, VCC = 2.0 V, and all other inputs held at VCC. The data retention test condition shall be held for 250 milliseconds before measurements. The data must remain valid after power is returned to device.