MIL-M-38510-57 Microcircuits, Digital, Cmos, Static Shift Register, Monolithic Silicon, Positive LogicThis specification covers the detail requirements for monolithic silicon, CMOS, logic microcircuits. Two product assurance classes and a choice of case outlines, lead finishes, and radiation hardness assurance RHA are provided and are reflected in the complete Part or Identifying Number PIN. For this product, the requirements of MIL-M-38510 have been superseded by MIL-PRF-38535 see 6.3.

Pages 1 - 2 - 3 - 4 - 5 - 6 - 7 - 8 - 9 - 10 - 11 - 12 - 13 - 14 - 15 - 16 - 17 - 18 - 19 - 20 - 21 - 22 - 23 - 24 - 25 - 26 - 27 - 28 - 29 - 30 - 31 - 32 - 33 - 34 - 35 - 36 - 37 - 38 - 39 - 40 - 41 - 42 - 43 - 44 - 45 - 46 - 47 - 48 - 49 - 50 - 51 - 52 - 53 - 54 - 55 - 56 - 57 - 58 - 59 - 60 - 61 - 62 - 63 - 64 - 65 - 66 - 67 - 68 - 69 - 70 - 71 - 72 - 73 - 74 - 75 - 76 - 77 - 78 - 79 - 80 - 81 - 82 - 83 - 84 - 85 - 86 - 87 - 88 - 89 - 90 - 91 - 92

MIL-M-38510157F

TABLE III. Group A inspection for device type 56 - Continued.

11 Pins not designated may be "HIGH" level logic, "LOW" level logic, or open. Exceptions are as follows: VIC(POS) tests, the VSS terminal shall be open; VIC(NEG) tests, the VDD terminal shall be open; ISS tests, the output terminals shall be open; IIH1 tests, the undesignated terminals shall be open.

21 In device type 56, circuit B, all terminals except 12 and 14, are inputs connected to gate structures; therefore, the table III, VIC(POS) and VIC(NEG) tests shall be expanded to include testing terminals 1 through 8 and 16 through 23.

31 The ISS test measurements shall be performed in sequence.

41 Apply clock pulse VIN = 0 V dc to VDD until proper output state is achieved.

51 VIH and VIL tests are performed by repeating the truth table tests (numbers 185 through 211) using the input and output conditions as follows:

Test	VDD	Input		Output
Test	VDD	H	L	H	L
VIH1 VIL1	5.0V	3.5V	1.5V	4.5V min	0.5V max
VIH2 VIL2	10.0V	7.0V	3.0V	9.0V min	1.0V max
VIH3 VIL3	15.0V	11.0V	4.0V	13.5V min	1.5V max

61 The device manufacturer may, at his option, measure IIL and IIH at 25°C for individual input or measure all inputs together.

71 See 4.4.1c.

81 The truth table tests shall be performed in sequence.

91 The truth table test shall be performed at VIH and VDD ≤ 5 V dc and � 18 V dc. L = VSS +0.50 V dc maximum and H = VDD -0.5 V dc minimum.

101 The maximum clock frequency (fCL) requirements are considered met if proper output state changes occur with the pulse repetition period set to that given in the limits column.