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MIL-M-38510-57 Microcircuits, Digital, Cmos, Static Shift Register, Monolithic Silicon, Positive LogicThis specification covers the detail requirements for monolithic silicon, CMOS, logic microcircuits. Two product assurance classes and a choice of case outlines, lead finishes, and radiation hardness assurance RHA are provided and are reflected in the complete Part or Identifying Number PIN. For this product, the requirements of MIL-M-38510 have been superseded by MIL-PRF-38535 see 6.3.

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TABLE III. Group A inspection for device type 53 - Continued.

Symbol

MIL- STD-

883 method

Cases

E,F,N,Z

Terminal conditions and limits 1/

Measured terminal

Test limits

Unit

Clock

Q4B

Q3A

Q2A

Q1A

Reset

Data

VSS

Clock

Q4A

Q3B

Q2B

Q1B

Reset

Data

VDD

Subgroup 9

TC = 25°C

Subgroup 10

TC = 125°C

Subgroup 11

TC = -55°C

Test no.

Min

Max

Min

Max

Min

Max

fCL

(max)

10/

161

162

163

164

165

166

167

168

IN "

" " " " "

OUT

GND "

" " " " "

IN "

" " " " "

GND "

" " " " "

IN "

" " " " "

OUT

GND "

" " " " "

IN "

" " " " "

5.0v

" " " " " " "

Clock A "

" "

Clock B "

.5 "

" " " " "

.667 "

" " " " "

.5 "

" " " " "

µs

" "

" " " "

1/ Terminals not designated may be "HIGH" level logic, "LOW" 5/ The device manufacturer may, at his option, measure IIL and IIH at level logic, or open except as follows: VIC(pos) tests; the VSS 25°C for each individual input or measure all inputs together. terminal shall be open. VIC(neg) tests; the VDD terminal shall 6/ See 4.4.1c.

be open. ISS test; the output terminal shall be open. 7/ Truth table test shall run in sequence.

2/ ISS test measurements shall be performed in sequence. 8/ The truth table test shall be performed at VIH and VDD ≤ 5.0 V dc and

3/ Apply a clock pulse; VIN = 0 V dc to VDD until proper output � 18.0 V dc.

state is achieved. 9/ The output voltage limits for each temperature are "H" = VDD -0.5 V

4/ VIH and VIL tests are performed by repeating the truth table min and "L" = VSS +0.5 V max.

tests (numbers 102 through 120) using the input conditions 10/ The maximum clock frequency (fCL) requirement is considered met if

as follows: proper output state changes occur with the pulse repetition period

set to that given in the limits column.

Test	VDD	Input		Output
Test	VDD	H	L	H	L
VIH1 VIL1	5.0V	3.5V	1.5V	4.5V min	0.5 max
VIH2 VIL2	10.0V	7.0V	3.0V	9.0V min	1.0V max
VIH3 VIL3	15.0V	11.0V	4.0V	13.5V min	1.5V max