An Integrated Publishing, Inc. Site

An Integrated Publishing Website

MIL-M-38510-57 Microcircuits, Digital, Cmos, Static Shift Register, Monolithic Silicon, Positive LogicThis specification covers the detail requirements for monolithic silicon, CMOS, logic microcircuits. Two product assurance classes and a choice of case outlines, lead finishes, and radiation hardness assurance RHA are provided and are reflected in the complete Part or Identifying Number PIN. For this product, the requirements of MIL-M-38510 have been superseded by MIL-PRF-38535 see 6.3.

Pages 1 - 2 - 3 - 4 - 5 - 6 - 7 - 8 - 9 - 10 - 11 - 12 - 13 - 14 - 15 - 16 - 17 - 18 - 19 - 20 - 21 - 22 - 23 - 24 - 25 - 26 - 27 - 28 - 29 - 30 - 31 - 32 - 33 - 34 - 35 - 36 - 37 - 38 - 39 - 40 - 41 - 42 - 43 - 44 - 45 - 46 - 47 - 48 - 49 - 50 - 51 - 52 - 53 - 54 - 55 - 56 - 57 - 58 - 59 - 60 - 61 - 62 - 63 - 64 - 65 - 66 - 67 - 68 - 69 - 70 - 71 - 72 - 73 - 74 - 75 - 76 - 77 - 78 - 79 - 80 - 81 - 82 - 83 - 84 - 85 - 86 - 87 - 88 - 89 - 90 - 91 - 92

TABLE III. Group A inspection for device type 54 - Continued.

Symbol

MIL- STD-

883 method

Cases

E,F,N,Z

Terminal conditions and limits 1/

Measured terminal

Test limits

Unit

PI8

PI4

PI3

PI2

PI1

VSS

P/S

control

Clock

Serial

PI5

PI6

PI7

VDD

Subgroup 9

TC = 25°C

Subgroup 10

TC = 125°C

Subgroup 11

TC = -55°C

Test no.

Min

Max

Min

Max

Min

Max

tTHL

3004

Fig. 4

138

139

140

OUT

GND "

IN "

OUT

5.0V "

13 "

210 "

18 "

280 "

13 "

210 "

" "

tTLH

141

142

143

OUT

" "

OUT

" "

fCL

(max)

11/

144

145

146

OUT

" " "

OUT

" " "

Clock Clock Clock

.75 "

1.0 "

.75 "

µs

1/ Terminals not designated may be "HIGH" level logic, "LOW" level logic, or open except as follows: VIC(pos) tests; the VSS terminal shall be open.

VIC(neg) tests; the VDD terminal shall be open. ISS tests; the output terminals shall be open.

2/ The ISS test measurements shall be performed in sequence.

3/ Apply clock pulse; VIN = 0 V dc to VDD until proper state is achieved.

4/ VIH and VIL tests are performed by repeating the truth table tests (numbers 89 through 125) using the input and output conditions as shown

below:

Test	VDD	Input		Output
Test	VDD	H	L	H	L
VIH1 VIL1	5.0V	3.5V	1.5V	Min 4.5V	Max 0.5V
VIH2 VIL2	10.0V	7.0V	3.0V	9.0V	1.0V
VIH3 VIL3	15.0V	11.0V	4.0V	13.5V	1.5V

5/ The device manufacturer may, at his option, measure IIL and IIH at 25°C for each individual input or measure all inputs together.

6/ See 4.4.1c.

7/ The truth table test shall be performed in sequence.

8/ Apply clock pulse, VIN = 0 V dc to VDD, tp = 500 ns (min), tTHL = 10 ns ± 10%.

9/ The output voltage limits for each temperature are "H" = VDD -0.5 V min and "L" = VSS +0.5 V max.

10/ The truth table tests shall be performed at VIH and VDD ≤ 5 V dc and ; 18 V dc.

11/ The maximum clock frequency (fCL) requirement is considered met if proper output state changes occur with the pulse repetition period set to

that given in the limits column.