MIL-M-38510-57 Microcircuits, Digital, Cmos, Static Shift Register, Monolithic Silicon, Positive LogicThis specification covers the detail requirements for monolithic silicon, CMOS, logic microcircuits. Two product assurance classes and a choice of case outlines, lead finishes, and radiation hardness assurance RHA are provided and are reflected in the complete Part or Identifying Number PIN. For this product, the requirements of MIL-M-38510 have been superseded by MIL-PRF-38535 see 6.3.

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TABLE III.  Group A inspection for device type 05 - Continued.

1/    Terminals not designated may be "HIGH" level logic, "LOW" level logic, or open except as follows: VIC(POS)  tests; the VSS  terminal shall be open.

VIC(NEG)  tests; the VDD  terminal shall be open.

ISS tests; the output terminals shall be open.

2/    Test numbers 9 through 76 shall be run in sequence.  See 4.5.3.

3/    Apply single clock pulse; VIN  = 0 V dc to VDD.

4/    VIL1 = 1.1 V at 25°C, 0.85 V at 125°C, 1.35 V at -55°C.

5/    Apply clock pulse; VIN  = 0 V to VDD  until proper output state is achieved.

6/    IOH1  = -320 µA at 25°C, -225 µA at 125°C, -400 µA at -55°C.

7/    IOH2  = -90 µA at 25°C, -60 µA at 125°C, -110µA at -55°C.

8/    IOH3  = -400 µA at 25°C, -280 µA at 125°C, -480µA at -55°C.

9/    VIH1  = 3.8 V at 25°C, 3.6 V at 125°C, 3.95 V at -55°C.

10/  VIL2 = 2.8 V at 25°C, 2.55 V at 125°C, 3.05 V at -55°C.

11/  VIH2  = 9.5 V at 25°C, 9.25 V at 125°C, 9.75 V at -55°C.

12/  IOL1 = 1.3 mA at 25°C, 0.5 mA at 125°C, 1.5 mA at -55°C.

13/  IOL2 = 90 µA at 25°C, 60 µA at 125°C, 110 µA at -55°C.

14/  IOL3 = 400 µA at 25°C, 280 µA at 125°C, 480 µA at -55°C.

15/  The device manufacturer may, at his option, measure IIL  and IIH  at 25°C for each individual input or measure all inputs together.

16/  See 4.4.1c.

17/  Test numbers 103 through 123 shall be run in sequence.

18/  The output voltage limits for each temperature are "H" = VDD  -0.5 V min. and "L" = VSS +0.5 V max.

19/  For all test conditions, delayed clock (CLD) is clock delayed by two inverters.

20/  The functional tests shall be performed at VIH  and VDD  ≤ 5.0 V and � 15 V.

21/  Apply 59 clock pulses; VIN  = 0 V dc to VDD.

22/  The maximum clock frequency (fCL) requirement is considered met if proper output state changes occur with the pulse repetition period set to that given in the limits column.