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MIL-M-38510-57 Microcircuits, Digital, Cmos, Static Shift Register, Monolithic Silicon, Positive LogicThis specification covers the detail requirements for monolithic silicon, CMOS, logic microcircuits. Two product assurance classes and a choice of case outlines, lead finishes, and radiation hardness assurance RHA are provided and are reflected in the complete Part or Identifying Number PIN. For this product, the requirements of MIL-M-38510 have been superseded by MIL-PRF-38535 see 6.3.

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TABLE III. Group A inspection for device type 03 - Continued.

Symbol

MIL- STD-

883 method

Cases

E,F,N,Z

Terminal conditions and limits 1/

Measured terminal

Test limits

Unit

Clock B

Q4B

Q3A

Q2A

Q1A

Reset A

Data A

VSS

Clock A

Q4A

Q3B

Q2B

Q1B

Reset B

Data B

VDD

Subgroup 9

TC = 25°C

Subgroup 10

TC = 125°C

Subgroup 11

TC = -55°C

Test no.

Min

Max

Min

Max

Min

Max

fCL

(max)

15/

139

140

141

142

143

144

145

146

IN "

" "

OUT

GND

" " " " " " "

" " "

GND

" " " " " " "

" " "

OUT

GND

" " " " " " "

IN "

" "

5.0V

" " " " " " "

Clock A

" " "

Clock B "

" "

1.0

" " " " " " "

1.4

" " " " " " "

1.0

" " " " " " "

µs

" " " " " " "

1/ Terminals not designated may be "HIGH" level logic, "LOW" level logic, or open except as follows: VIC(POS) tests; the VSS terminal shall be open.

VIC(NEG) tests; the VDD terminal shall be open. ISS tests; the output terminals shall be open.

2/ Test numbers 13 through 27 shall be run in sequence. See 4.5.3.

3/ Apply clock pulse; VIN = 0 V to VDD until proper output state is achieved.

4/ IOH = -80 µA at 25°C, -55 µA at 125°C, -100 µA at -55°C.

5/ VIL1 = 1.1 V at 25°C, 0.85 V at 125°C, 1.35 V at -55°C.

6/ VIH1 = 3.8 V at 25°C, 3.6 V at 125°C, 3.95 V at -55°C.

7/ VIL2 = 2.8 V at 25°C, 2.55 V at 125°C, 3.05 V at -55°C.

8/ VIH2 = 9.5 V at 25°C, 9.25 V at 125°C, 9.75 V at -55°C.

9/ IOL = 120 µA at 25°C, 85 µA at 125°C, 150 µA at -55°C.

10/ The device manufacturer may, at his option, measure IIL and IIH at 25°C for each individual input or measure all inputs together.

11/ See 4.4.1c.

12/ Test numbers 80 through 98 shall be run in sequence.

13/ The output voltage limits for each temperature are "H" = VDD -0.5 V min. and "L" = VSS +0.5 V max.

14/ The functional tests shall be performed at VIH and VDD ≤ 5.0 V and ; 15 V.

15/ The maximum clock frequency (fCL) requirement is considered met if proper output state changes occur with the pulse repetition period set to that given in the limits column.