MIL-M-38510-57 Microcircuits, Digital, Cmos, Static Shift Register, Monolithic Silicon, Positive LogicThis specification covers the detail requirements for monolithic silicon, CMOS, logic microcircuits. Two product assurance classes and a choice of case outlines, lead finishes, and radiation hardness assurance RHA are provided and are reflected in the complete Part or Identifying Number PIN. For this product, the requirements of MIL-M-38510 have been superseded by MIL-PRF-38535 see 6.3.

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TABLE III. Group A inspection for device type 55 - Continued.

1/	Terminals not designated may be "HIGH" level logic, "LOW" level logic, or open except as follows: VIC(POS) tests; the VSS terminal	10/	The output voltage limits for each temperature are "H" = VDD -0.5 V min and "L" = VSS +0.5 V max.
	shall be open. VIC(NEG) tests; the VDD terminal shall be open. ISS	11/	The functional test shall be performed at VIH and VDD s 5.0 V dc and
	test, the output terminal shall be open.		� 18.0 V dc.
2/	The ISS tests shall be performed in sequence.	12/	Apply 59 clock pulses: VIN = 0 V dc to VDD, tp = 500 ns (min) and
3/	Apply a single clock pulse; VIN = 0 V dc to VDD.		tTLH = tTHL = 10 ns ± 10%.
4/	Apply clock pulse: VIN = 0 V dc to VDD, until proper output state	13/	The maximum clock frequency (fCL) requirement is considered met if
	is achieved.		proper output state changes occur with the pulse repetition period
5/	VIH and VIL tests are performed by repeating the truth table tests		set to that given in the limits column.
	(numbers 115 through 135) using the input and output conditions
	as follows:

6/ The device manufacturer may, at his option, measure IIL and IIH at

25°C for each individual input or measure all inputs together.

7/ See 4.4.1c.

8/ Test numbers 115 through 135 shall be run in sequence.

9/ For all test conditions, delayed clock (CLD) is clock delayed by two inverters.