TABLE III. Group A inspection for device type 01 - Continued.
1/ Terminals not designated may be "HIGH" level logic, "LOW" level logic, or open except as follows: VIC(POS) tests; the VSS terminal shall be open.
VIC(NEG) tests; the VDD terminal shall be open. ISS tests; the output terminals shall be open.
2/ Test numbers 11 through 19 shall be run in sequence. See 4.5.3.
3/ Apply single clock pulse; VIN = 0 V to VDD.
4/ VIH1 = 3.8 V at 25°C, 3.6 V at 125°C, 3.95 V at -55°C.
5/ Apply clock pulse; VIN = 0 V to VDD until proper output state is achieved.
6/ IOH = -100 µA at 25°C, -70 µA at 125°C, -125 µA at -55°C.
7/ VIH2 = 9.5 V at 25°C, 9.25 V at 125°C, 9.75 V at -55°C.
8/ VIL1 = 1.1 V at 25°C, 0.85 V at 125°C, 1.35 V at -55°C.
9/ IOL = 125 µA at 25°C, 85 µA at 125°C, 155 µA at -55°C.
10/ VIL2 = 2.8 V at 25°C, 2.55 V at 125°C, 3.05 V at -55°C.
11/ The device manufacturer may, at his option, measure IIL and IIH at 25°C for each individual input or measure all inputs together.
12/ See 4.4.1c.
13/ Test numbers 61 through 76 shall be run in sequence.
14/ Apply single clock pulse; VIN = 0 V to VDD.
15/ The output voltage limits for each temperature are "H" = VDD -0.5 V min. and "L" = VSS +0.5 V max.
16/ The functional tests shall be performed at VIH and VDD ≤ 5.0 V and � 15 V.
17/ The maximum clock frequency (fCL) requirement is considered met if proper output state changes occur with the pulse repetition period set to that given in the limits column.
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