MIL-M-38510-57 Microcircuits, Digital, Cmos, Static Shift Register, Monolithic Silicon, Positive LogicThis specification covers the detail requirements for monolithic silicon, CMOS, logic microcircuits. Two product assurance classes and a choice of case outlines, lead finishes, and radiation hardness assurance RHA are provided and are reflected in the complete Part or Identifying Number PIN. For this product, the requirements of MIL-M-38510 have been superseded by MIL-PRF-38535 see 6.3.

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TABLE III. Group A inspection for device type 51 - Continued.

11 Terminals not designated may be "HIGH" level logic, "LOW" level logic, or open except as follows: VIC(pos) tests; the VSS terminal shall be open.

VIC(neg) tests; the VDD terminal shall be open.

ISS tests; the output terminals shall be open.

21 The ISS test measurements shall be run in sequence.

31 Apply single clock pulse; VIN = 0 V to VDD.

41 Apply clock pulse; VIN = 0 V dc to VDD until proper output state is achieved.

51 VIH and VIL tests are performed by repeating the truth table test (numbers 79 through 94) using the input and output conditions as follows:

Test	VDD	Input levels		Output levels
Test	VDD	H	L	H	L
VIL1 VIH1	5.0V	3.5V	1.5V	Min 4.5V	Max 0.5V
VIL2 VIH2	10.0V	7.0V	3.0V	9.0V	1.0V
VIL3 VIH3	15.0V	11.0V	4.0V	13.5V	1.5V

61 The device manufacturer may, at his option, measure IIL and IIH at 25°C for each individual input or measure all inputs together.

71 See 4.4.1c.

81 The truth table test shall be performed in sequence.

91 The truth table tests shall be performed at VIH and VDD ≤ 5 V dc and ; 18 V dc.

L = VSS +0.5 V maximum, and H = VDD -0.50 V dc minimum.

101 The maximum clock frequency (fCL) requirement is considered met if proper output state changes occur with the pulse repetition period set to that given in the limits column.

111 The device manufacturer may perform VIL1VIH tests as functional tests.