MIL-M-38510/57F
Device types 04 and 54
| Inputs | Output | |||||
| CL (level change) | Serial input | Parallel/serial control | PI-1 | PI-n | Q1 (internal) | Qn | 
| x | x | 1 | 0 | 0 | 0 | 0 | 
| x | x | 1 | 0 | 1 | 0 | 1 | 
| x | x | 1 | 1 | 0 | 1 | 0 | 
| x | x | 1 | 1 | 1 | 1 | 1 | 
| t | 0 | 0 | x | x | 0 | Qn-1 | 
| t | 1 | 0 | x | x | 1 | Qn-1 | 
| ↓ | x | 0 | x | x | Q1 | Qn | 
Positive logic 0 � VSS. Positive logic 1 � VDD.
↓ = Clock transition from high to low.
t = Clock transition from low to high. x = Don't care.
Device types 05 and 55
INPUT CONTROL CIRCUIT TRUTH TABLE TYPICAL STAGE TRUTH TABLE
| DATA | RECIRC. | MODE | BIT INTO STAGE 1 | 
| 1 | x | 0 | 1 | 
| 0 | x | 0 | 0 | 
| x | 1 | 1 | 1 | 
| x | 0 | 1 | 0 | 
Device types 06 and 56
| "A" Enable | P/S | A/B | A/S | Operation * | 
| L | L | L | x | Serial mode; synch. serial data input, "A" parallel data outputs disabled | 
| L | L | H | x | Serial mode; synch. serial data input, "B" parallel data output | 
| L | H | L | L | Parallel mode; "B" synch. parallel data inputs, "A" parallel data outputs disabled | 
| L | H | L | H | Parallel mode; "B" asynch. parallel data inputs, "A" parallel data outputs disabled | 
| L | H | H | L | Parallel mode; "A" parallel data inputs disabled, "B" parallel data outputs, synch. data recirculation | 
| L | H | H | H | Parallel mode; "A" parallel data inputs disabled, "B" parallel data outputs, asynch. data recirculation | 
| H | L | L | x | Serial mode; synch. serial data input, "A" parallel data output | 
| H | L | H | x | Serial mode; synch. serial data input, "B" parallel data output | 
| H | H | L | L | Parallel mode; "B" synch. parallel data input, "A" parallel data output | 
| H | H | L | H | Parallel mode; "B" asynch. parallel data input, "A" parallel data output | 
| H | H | H | L | Parallel mode; "A" synch. parallel data input, "B" parallel data output | 
| H | H | H | H | Parallel mode; "A" asynch. parallel data input, "B" parallel data output | 
* Outputs change at positive transition of clock in the serial mode and when the A/S/ control input is "low" in the parallel mode.
Positive logic 0 � VSS. Positive logic 1 � VDD. NC = No change.
↓ = Clock transition from high to low.
t = Clock transition from low to high. x = Don't care.
FIGURE 3. Truth tables - Continued.
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