TABLE III. Group A inspection for device type 52 - Continued.
Symbol |
MIL- STD- 883 method |
Cases E,F,N,Z |
Terminal conditions and limits 1/ |
Measured terminal |
Test limits |
Unit |
||||||||||||||||||||
PI8 |
Q6 |
Q8 |
PI4 |
PI3 |
PI2 |
PI1 |
VSS |
P/S control |
Clock |
Serial In |
Q7 |
PI5 |
PI6 |
PI7 |
VDD |
Subgroup 9 TC = 25°C |
Subgroup 10 TC = 125°C |
Subgroup 11 TC = -55°C |
||||||||
Test no. |
1 |
2 |
3 |
4 |
5 |
6 |
7 |
8 |
9 |
10 |
11 |
12 |
13 |
14 |
15 |
16 |
Min |
Max |
Min |
Max |
Min |
Max |
||||
tPHL1 |
3003 Fig. 4 |
140 141 142 |
IN IN IN |
OUT |
OUT |
IN IN IN |
IN IN IN |
IN IN IN |
IN IN IN |
GND GND GND |
GND GND GND |
IN IN IN |
IN IN IN |
OUT |
IN IN IN |
IN IN IN |
IN IN IN |
5.0V 5.0V 5.0V |
Clock to Q6 Clock to Q7 Clock to Q8 |
13 " " |
338 " " |
18 " " |
450 " " |
13 " " |
338 " " |
ns ns ns |
tPLH1 |
3003 Fig. 4 |
143 144 145 |
IN " " |
OUT |
OUT |
IN " " |
IN " " |
IN " " |
IN " " |
GND " " |
GND GND GND |
IN " " |
IN " " |
OUT |
IN " " |
IN " " |
IN " " |
5.0V " " |
Clock to Q6 Clock to Q7 Clock to Q8 |
13 " " |
338 " " |
18 " " |
450 " " |
13 " " |
338 " " |
ns " " |
tPHL2 |
146 147 148 |
" " " |
OUT |
OUT |
" " " |
" " " |
" " " |
" " " |
" " " |
5.0V " " |
" " " |
" " " |
OUT |
" " " |
" " " |
" " " |
" " " |
Clock to Q6 Clock to Q7 Clock to Q8 |
" " " |
" " " |
" " " |
" " " |
" " " |
" " " |
" " " |
|
tPLH2 |
149 150 151 |
" " " |
OUT |
OUT |
" " " |
" " " |
" " " |
" " " |
" " " |
" " " |
" " " |
" " " |
OUT |
" " " |
" " " |
" " " |
" " " |
Clock to Q6 Clock to Q7 Clock to Q8 |
" " " |
" " " |
" " " |
" " " |
" " " |
" " " |
" " " |
|
tTHL |
3004 Fig. 4 |
152 153 154 |
" " " |
OUT |
OUT |
" " " |
" " " |
" " " |
" " " |
" " " |
" " " |
" " " |
" " " |
OUT |
" " " |
" " " |
" " " |
" " " |
Q6 Q7 Q8 |
10 " " |
210 " " |
14 " " |
280 " " |
10 " " |
210 " " |
" " " |
tTLH |
155 156 157 |
" " " |
OUT |
OUT |
" " " |
" " " |
" " " |
" " " |
" " " |
" " " |
" " " |
" " " |
OUT |
" " " |
" " " |
" " " |
" " " |
Q6 Q7 Q8 |
" " " |
" " " |
" " " |
" " " |
" " " |
" " " |
" " " |
|
fCL (max) 11/ |
158 159 160 |
OUT |
OUT |
" " " |
GND GND GND |
" " " |
" " " |
OUT |
" " " |
Clock Clock Clock |
.625 " " |
.833 " " |
.625 " " |
µs µs µs |
||||||||||||
1/ Terminals not designated may be "HIGH" level logic, "LOW" level logic, or open except as follows: VIC(pos) tests; the VSS terminal shall be open.
VIC(neg) tests; the VDD terminal shall be open. ISS test; the output terminal shall be open.
2/ ISS tests; the output terminals shall be performed in sequence.
3/ Apply a single clock pulse; VIN = 0 V dc to VDD.
4/ VIH and VIL tests are performed by repeating the truth table test (numbers 92 through 139) using the input and output conditions as follows:
Test |
VDD |
Input |
Output |
||
H |
L |
H |
L |
||
VIH1 VIL1 |
5.0V |
3.5V |
1.5V |
4.5V min |
0.5V max |
VIH2 VIL2 |
10.0V |
7.0V |
3.0V |
9.0V min |
1.0V max |
VIH3 VIL3 |
15.0V |
11.0V |
4.0V |
13.5V min |
1.5V max |
5/ The device manufacturer may, at his option, measure IIL and IIH at 25°C for each individual input or measure all inputs together.
6/ Apply six (6) clock pulses, VIN = 0 V dc to VDD.
7/ See 4.4.1c.
8/ Truth table test shall be run in sequence.
9/ The output voltage limits for each temperature are "H" = VDD -0.5 V min and "L" = VSS +0.5 V max.
10/ The truth table tests shall be performed at VIH and VDD ≤ 5 V dc and ; 18 V dc.
11/ The maximum clock frequency (fCL) requirement is considered met if proper output state changes occur with the pulse repetition period set to
that given in the limits column.
12/ The device manufacturer may perform VIL/VIH tests as functional tests.
For Parts Inquires call Parts Hangar, Inc (727) 493-0744
© Copyright 2015 Integrated Publishing, Inc.
A Service Disabled Veteran Owned Small Business