MIL-M-38510-245 Microcircuits, Digital, Cmos, 4096 Bit, Static Random Access Memory Sram, Bulk Silicon And Silicon On SapphireThis specification covers the detail requirements for bulk silicon and silicon on sapphire SOS, static, 4096 bit, random access memory microcircuits. Two product assurance classes, four radiation hardness assurance levels, and a choice of case outlines and lead finishes are provided and are reflected in the part number. For this product, the requirements of MIL-M-38510 have been superseded by MIL-PRF-38535, see 6.4

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MIL-M-38510/245B

i.     Requirements for "JAN" marking.

j.     Packaging Requirements (see 5.1)

6.3  Qualification.  With respect to products requiring qualification, awards will be made only for products which are, at the time of award of contract, qualified for inclusion in Qualified Manufacturers List QML-38535 whether or not such products have actually been so listed by that date.  The attention of the contractors is called to these requirements, and manufacturers are urged to arrange to have the products that they propose to offer to the Federal Government tested for qualification in order that they may be eligible to be awarded contracts or purchase orders for the products covered by this specification.  Information pertaining to qualification of products may be obtained from DSCC-VQ, 3990 E. Broad Street, Columbus, Ohio 43218-3990.

6.4  Superseding information.  The requirements of MIL-M-38510 have been superseded to take advantage of the available Qualified Manufacturer Listing (QML) system provided by MIL-PRF-38535.  Previous references to MIL-M-

38510 in this document have been replaced by appropriate references to MIL-PRF-38535.  All technical requirements now consist of this specification and MIL-PRF-38535.  The MIL-M-38510 specification sheet number and PIN have

been retained to avoid adversely impacting existing government logistics systems and contractor's parts lists.

6.5  Abbreviations, symbols, and definitions.  The abbreviations, symbols, and definitions used herein are defined in MIL-PRF-38535, MIL-HDBK-1331, and as follows:

CI ................................................. Input capacitance.

IDD   ISS .......................................... Quiescent supply current

IDDOP............................................. Operating supply current

II ................................................... Input leakage current.

IOH ................................................ Logical high output current.

IOL ................................................ Logical low output current.

IOZ ................................................ Output leakage current.

VDD............................................... Supply voltage

VDDR ............................................. Data retention supply voltage.

VIH ................................................ Logical high input voltage.

VIL ................................................ Logical low input voltage.

VOH............................................... Logical high output voltage.

VOL ............................................... Logical low output voltage.

tAVEL.............................................. Address setup time.

tAVQV ............................................. Address access time

tAVWH............................................. Address to end of write setup time.

tAVWL ............................................. Address setup to start of write time.

tDVEL ............................................. Write data setup time.

tDVWH ............................................ Data setup time.

tELQV ............................................. Chip enable access time.

tWHEL............................................. Write enable high to chip enable low.

tWLEL ............................................. Write enable pulse setup time to chip enable.

tELQX ............................................. Chip enable output enable time.

tWLQZ............................................. Write enable output disable time.

tEHQZ ............................................. Chip enable output disable time.

tEHWH ............................................ Output high-Z time.

tELDX ............................................. Write data hold time.

tQVWL............................................. Data valid to write time.

tELEH ............................................. Chip enable pulse negative width.

tEHEL ............................................. Chip enable pulse positive width.

tELAX.............................................. Address hold time.

tWLWH ............................................ Write enable pulse negative width

tWLEH............................................. Write enable pulse setup time to chip enable.

tELWH............................................. Write enable pulse hold time from chip enable.

tWHDX ............................................ Data hold time.

tELEL.............................................. Read or write cycle time.

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