MIL-M-38510-245 Microcircuits, Digital, Cmos, 4096 Bit, Static Random Access Memory Sram, Bulk Silicon And Silicon On SapphireThis specification covers the detail requirements for bulk silicon and silicon on sapphire SOS, static, 4096 bit, random access memory microcircuits. Two product assurance classes, four radiation hardness assurance levels, and a choice of case outlines and lead finishes are provided and are reflected in the part number. For this product, the requirements of MIL-M-38510 have been superseded by MIL-PRF-38535, see 6.4

Pages 1 - 2 - 3 - 4 - 5 - 6 - 7 - 8 - 9 - 10 - 11 - 12 - 13 - 14 - 15 - 16 - 17 - 18 - 19 - 20 - 21 - 22 - 23 - 24 - 25 - 26 - 27 - 28 - 29 - 30 - 31 - 32 - 33 - 34 - 35 - 36 - 37 - 38 - 39 - 40 - 41 - 42 - 43 - 44 - 45 - 46 - 47 - 48 - 49 - 50 - 51 - 52 - 53 - 54 - 55 - 56 - 57 - 58 - 59 - 60 - 61 - 62 - 63 - 64 - 65 - 66 - 67 - 68 - 69 - 70 - 71 - 72 - 73 - 74 - 75 - 76 - 77 - 78

MIL-M-38510/2458

1/  Pins not designated may be high level logic or low level logic.  Exceptions are as follows:  VIC(pos) test, the VSS terminal shall be open, or if tester limitations prevent open, the GND condition is permitted; VIC(neg)  tests, the VDD terminal shall be open;  IDD  test, the output terminal shall be open.

2/  Contents of addressed cell shall be data 0, IOL  = 2 mA for VOL  measurements, or VOL = 0.4 V for IOL

measurements.

3/  Contents of addressed cell shall be data 1, IOH  = -1 mA for VOH  measurements, or VOH  = 4.35 V for IOH

measurements.

4/  The device manufacturer may, at his option, measure IIL  and IIH  at +25°C for each individual input or measure all inputs together.

5/  Fill memory with checkerboard data pattern.

6/  Fill memory with 1's.

7/  Fill memory with 0's.

8/  See 4.4.1c.

9/  Power down test (PWRDWN) terminal conditions shall be as follows:

a.   Use load specified on figure 3.

b.   The power down test shall be performed as follows: (1)   Power up RAM to full functional voltage.

(2)   Write topologically true checkboard pattern into RAM memory array.

(3)   Reduce VDD  to required voltage.  All device inputs shall be reduced along with VDD, exercising special care to avoid latch-up.

(4)   Maintain RAM at reduced voltage.

(5)   Measure the leakage current during this period. (6)   Raise VDD  to full functional voltage.

(7)   Verify RAM contents to be unchanged from pattern written in (2) above. (8)   Repeat steps (1) through (6) using the inverse checkerboard pattern.

10/  Functional test terminal conditions shall be as follows:

a.  Use timing parameter and limits specified on figure 5. b.  Use several patterns (see appendix).

c.   Use load specified on figure 3.

d.  VDD  per appropriate type, see table III; VIL = VSS; VIH = VDD.

11/  Timing test terminal conditions shall be as follows:

a.  Use timing parameter and limits specified on figure 5. b.  Use pattern of choice.

c.   Use load specified on figure 3.

d.  VDD  per appropriate type, see table III; VIL = VSS; VIH = VDD.

12/  Operating current test (IDDOP) terminal conditions shall be as follows:

a.   Period = 1 µs using a write cycle loop during measurement. b.   Use topologically true checkerboard pattern (see appendix).

c.   VIL  = 0 V; VIH = 5.5 V for device types 01 to 04, VIH = 5.25 V for device types 05 and 06.

13/  Inverse checkerboard data pattern.

14/  Guaranteed but not tested.

67