MIL-M-38510-245 Microcircuits, Digital, Cmos, 4096 Bit, Static Random Access Memory Sram, Bulk Silicon And Silicon On SapphireThis specification covers the detail requirements for bulk silicon and silicon on sapphire SOS, static, 4096 bit, random access memory microcircuits. Two product assurance classes, four radiation hardness assurance levels, and a choice of case outlines and lead finishes are provided and are reflected in the part number. For this product, the requirements of MIL-M-38510 have been superseded by MIL-PRF-38535, see 6.4

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MIL-M-38510/2458

TRUTH TA8LE

Time reference	Inputs			Data I/O	Function
Time reference	CE	w	A	DQ	Function
-1	H	x	x	z	Memory disable
0		H	v	z	Cycle begins, addresses are latched
1	L	H	x	x	Output enabled
2	L	H	x	v	Output valid
3		H	x	v	Read accomplished
4	H	x	x	z	Prepare for next cycle (same as -1)
5		H	v	z	Cycle ends, next cycle begins (same as 0)

The address information is latched in on the chip registers on the falling edge of CE (T = 0). Minimum address setup and hold time requirements must be met. After the required hold time, the addresses may change state without affecting device operation. During time (T = 1), the outputs become enabled but data is not valid until time (T = 2).

w must remain high throughout the read cycle. After the data has been read, CE may return high (T = 3). This will force the output buffers into a high impedance mode at time (T = 4). The memory is now ready for the next cycle.

NOTE: See figure 5 for test conditions.

FIGURE 4. Read cycle, write cycle, read/modify/write cycle wave forms and truth tables - Continued.