MIL-M-38510-245 Microcircuits, Digital, Cmos, 4096 Bit, Static Random Access Memory Sram, Bulk Silicon And Silicon On SapphireThis specification covers the detail requirements for bulk silicon and silicon on sapphire SOS, static, 4096 bit, random access memory microcircuits. Two product assurance classes, four radiation hardness assurance levels, and a choice of case outlines and lead finishes are provided and are reflected in the part number. For this product, the requirements of MIL-M-38510 have been superseded by MIL-PRF-38535, see 6.4

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MIL-M-38510/2458

Timing parameter	Description	Device types
		03		04		05		06		Unit
		Min	Max	Min	Max	Min	Max	Min	Max
tELQV	Chip enable access time		300		300		280		280	ns
tAVQV	Address access time		320		320		250		250	ns
tELQX	Chip enable output enable time		50		50			20		ns
tWLQZ	Write enable output disable time				100					ns
tELEH	Chip enable pulse negative width	300		300		220		200		ns
tEHEL	Chip enable pulse positive width	120		120						ns
tAVEL	Address setup time	20		20						ns
tELAX	Address hold time	50		100						ns
tWHAX	Address hold time					45		40		ns
tWLWH	Write enable pulse negative width	80		300		145		150		ns
tWLEH	Write enable pulse setup time to chip disable	200		300						ns
tWLEL	Write enable pulse setup time to chip enable	0		0						ns
tELWH	Write enable pulse hold time from chip enable	80		300						ns
tELDX	Write data hold time	80								ns
tDVWH	Data setup time			200		120		105		ns
tWHDX	Data hold time			30		10		5		ns
tELEL	Read or write cycle time	420		420						ns
tAVAV	Read or write address cycle time					250		250		ns
tDVEL	Write data setup time	0								ns
tWHEH	Write enable high to chip enable high	0								ns
tELWL	Write output high-Z time	0		0						ns
tQVWL	Data valid to write time	0		0						ns
tEHWH	Output high-Z time	0		0						ns
tDVWL	Data setup time	0								ns
tWLDX	Data hold time	80								ns
tELDX	Early write data	80								ns
tWLDV	Write data delay time			100						ns
tWHEL	Write enable read mode setup time	0								ns
tAVWH	Address setup to end write time					205		200		ns

FIGURE 5. Timing test conditions over operating temperature range - Continued.