MIL-M-38510-245 Microcircuits, Digital, Cmos, 4096 Bit, Static Random Access Memory Sram, Bulk Silicon And Silicon On SapphireThis specification covers the detail requirements for bulk silicon and silicon on sapphire SOS, static, 4096 bit, random access memory microcircuits. Two product assurance classes, four radiation hardness assurance levels, and a choice of case outlines and lead finishes are provided and are reflected in the part number. For this product, the requirements of MIL-M-38510 have been superseded by MIL-PRF-38535, see 6.4

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MIL-M-38510/2458

TRUTH TA8LE

Time reference	Inputs				Output	Function
Time reference	CE	W	A	D	Q	Function
-1	H	x	x	x	z	Memory disable
0		H	v	x	z	Cycle begins, addresses are latched
1	L	H	x	x	x	Output enabled
2	L	H	x	x	v	Output valid, read and modify time
3	L		x	v	v	Write begins, data is latched
4	L	x	x	x	v	Write in progress internally
5		x	x	x	v	Write completed
6	H	x	x	x	z	Prepare for next cycle (same as -1)
7		H	v	x	z	Cycle ends, next cycle begins (same as 0)

The read/modify/write cycle begins as all other cycles on the falling edge of CE (T = 0). The W line should be high at (T = 0)

in order to latch the output buffers in the active state. During (T = 1) the output will be active but not valid until (T = 2). On the falling edge of the W (T = 3), the data present at the output and input are latched. The W signal also latches itself on its' low going edge. All input signals excluding CE have been latched and have no further effect on the SRAM. The rising edge of

CE (T = 5) completes the write portion of the cycle and unlatches all inputs and the output. The output goes to a high impedance and the SRAM is ready for the next cycle.

NOTE: See figure 5 for test conditions.

FIGURE 4. Read cycle, write cycle, read/modify/write cycle waveforms and truth tables - Continued.