MIL-M-38510/2458
TRUTH TA8LE
Time reference |
Inputs |
Data I/0 |
Function |
||
CE |
W |
A |
DQ |
||
-1 |
H |
x |
x |
z |
Memory disable |
0 |
x |
v |
z |
Cycle begins, addresses are latched |
|
1 |
L |
L |
x |
z |
Write period begins |
2 |
L |
x |
v |
Data in is written |
|
3 |
H |
x |
z |
Write completed |
|
4 |
H |
x |
x |
z |
Prepare for next cycle (same as -1) |
5 |
H |
v |
z |
Cycle ends, next cycle begins (same as 0) |
|
The write cycle is initiated on the falling edge of CE (T = 0), which latches the address information in on chip registers. If a dedicated write cycle is to be performed and the outputs are not to become active, tWLEL and tEHWH must be met. Under these conditions, tWLDv is unnecessary and input data may be applied at any convenient time as long as tDvWH is still met. If tWLEL is not met, then the outputs may become enabled momentarily near the beginning of the cycle and a disable time (tELQz) must be met before the input data is applied (tWLQz = tWLDv). Similiarly, if tEHWH is not met the outputs
may enable briefly near the end of the cycle.
The write operation is terminated by the first rising edge of W (T = 2) or CE (T = 3). After the minimum required CE
high time (tEHEL), the next cycle may begin. If a series of consecutive write cycles are to be performed, the W line may be held low until all desired location have been written. In this case, data setup and hold times must be referenced to
the rising edge of CE .
N0TE: See figure 5 for test conditions.
FIGURE 4. Read cycle, write cycle, read/modify/write cycle waveforms and truth tables - Continued
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