MIL-M-38510-245 Microcircuits, Digital, Cmos, 4096 Bit, Static Random Access Memory Sram, Bulk Silicon And Silicon On SapphireThis specification covers the detail requirements for bulk silicon and silicon on sapphire SOS, static, 4096 bit, random access memory microcircuits. Two product assurance classes, four radiation hardness assurance levels, and a choice of case outlines and lead finishes are provided and are reflected in the part number. For this product, the requirements of MIL-M-38510 have been superseded by MIL-PRF-38535, see 6.4

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MIL-M-38510/2458

TRUTH TA8LE

Time reference	Inputs				Output	Function
Time reference	CE	W	A	D	Q	Function
-1	H	x	x	x	z	Memory disable
0		L	v	v	z	Cycle begins, addresses are latched
1	L	x	x	x	z	Write in progress internally
2		x	x	x	z	Write completed
3	H	x	x	x	z	Prepare for next cycle (same as -1)
4		L	v	v	z	Cycle ends, next cycle begins (same as 0)

The early write cycle is the only cycle where the output is guaranteed not to become active. On the falling edge of CE (T = 0), the addresses, the write signal, and the data input are latched in on chip registers. The logic value of W at the time CE falls determines the state of the output buffer for that cycle. Since W is low in the early write cycle, the output buffer is latched into the high impedance state and will remain in the state until CE returns high (T = 2). For this cycle, the data input is latched by

CE going low; therefore data set up and hold times should be referenced to CE . When CE (T = 2) returns to the high state, the output buffer disables and signals are unlatched. The device is now ready for the next cycle.

NOTE: See figure 5 for test conditions.

FIGURE 4. Read cycle, write cycle, read/modify/write cycle waveforms and truth tables - Continued.