MIL-M-38510/210F
f. The outputs should be programmed one output at a time, since the internal decoding circuitry is capable of sinking only one unit of programming current at a time. Note that the PROM is supplied with fuses generating a low-level logic output. Programming a fuse will cause the output to go to a high level logic in the verify mode.
g. Repeat 4.16b through 4.16f for all other bits to be programmed.
h. If any bit does not verify as programmed, it shall be considered a programming reject.
4.17 Programming procedures for circuit J. The programming characteristics in table IVJ and the following procedures shall be used for programming the device:
a. Connect the device in the electrical configuration for programming. The waveforms on figure 5J and the programming characteristics of table IVJ shall apply to these procedures.
b. Address the PROM with the binary address of the selected word to be programmed. Address inputs are TTL compatible. An open circuit should not be used to address the PROM.
c. Disable the chip by applying input high (VIH) to the CS input. CS input must remain at VIH for programming. The chip select is TTL compatible. An open circuit should not be used to disable the chip.
d. Disable the programming circuitry by applying an Output Voltage Disable of less than VOPD to the output of the PROM. The output may be left open to achieve the disable.
e. Raise VCC to VPH with rise time equal to tr.
f. After a delay equal to or greater than td, apply a pulse with amplitude of VOPE and duration of tP to the output selected for programming. Note that the PROM is supplied with fuses intact generating an output high. Programming a fuse will cause the output to go low in the verify mode.
g. Other bits in the same word may be programmed while the VCC input is raised to VPH by applying output enable pulses to each output which is to be programmed. The output enable pulses must be separated
by a minimum interval of td.
h. Lower VCC to 4.5 V following a delay of td from the last programming enable pulse applied to an output. i. Enable the PROM for verification by applying a logic "O" (VIL) to the CS input.
j. Repeat 4.17a through 4.17i for all other bit to be programmed in the PROM.
k. If any bit does not verify as programmed, it shall be considered a programming reject.
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