MIL-M-38510/210F
4.15 Programming procedures for circuit H. The programming characteristics of table IVH and the following procedures shall be used for programming the device.
a. Connect the device in the electrical configuration for programming. The waveforms on figure 5H and the programming characteristics of table IVH shall apply to these procedures.
b. Address the word to be programmed, apply 5 V to VCC and active levels to all chip Enable inputs. c. Verify the status of a bit location by checking the output level.
d. Decrease VCC to 0 V.
e. For bit locations that do not require programming, skip steps 4.15f through 4.15l. f. Increase VCC to VCC(pr) with a minimum current capability of 250 mA.
g. Apply VS(pr) to all chip Enable inputs. II ≤ 25 mA. Active-high enables may be left high.
h. Connect all outputs, except the one to be programmed, to VIL. Only one bit is to be programmed at a time.
i. Apply the output programming pulse for 20 ∝s. Minimum current capability of the programming supply should be 250 mA.
j. After terminating the output pulse, disconnect all outputs from VIL conditions. k. Reduce the voltage at CE input to VIL.
l. Decrease VCC to 0 V.
m. Return to 4.15e until all outputs in the word have been programmed. n. Repeat 4.15c through 4.15l for each word in memory.
o. Verify programming of every word after all words have been programmed using VCC values of 4.5 V and
5.5 V.
p. If any bit does not verify as programmed, it shall be considered a programming reject.
4.16 Programming procedures for circuit I. The programming characteristics in table IVI and the following procedures shall be used for programming the device:
a. Connect the device in the electrical configuration for programming. The waveforms on figure 5I and the programming characteristics of table IVI shall apply to these procedures.
b. Terminate all outputs with a 300 ν resistor to VONP. Apply VIHP to the CE 2, CE3, and CE4 inputs and
VILP to the CE 1 inputs.
c. Address the PROM with the binary address of the selected word to be programmed. Raise VCC to VCCP. d. After a delay of t1, apply only one VOP pulse with a duration of tP, t2 and d(VOP)/dt to the output selected
for programming. After a delay of t2 and d(VOP)/dt, pulse CE 2 from VIHP to VCEP for the duration of tP,
2d(VCE)/dt, and t3; CE 2 is then to go to VILP level.
e. To verify programming after CE 1 has been set to VILP, lower VCC to VCCL after a delay of t4. The
programmed output should remain in the logic '1' state.
13
For Parts Inquires call Parts Hangar, Inc (727) 493-0744
© Copyright 2015 Integrated Publishing, Inc.
A Service Disabled Veteran Owned Small Business