MIL-M-38510/210F
h. Return the CE 2 to VIH.
i. Wait TD5 and lower VCC to VCCV.
j. Wait TD6 and lower CE 2 to VIL for the duration to TV.
k. A properly blown fuse will read VOL and unblown fuse will read VOH.
1. If the fuse is blown, go to n.
2. If the fuse is unblown, go to 1.
l. If TP is less than 30 µs, increment TP by 5 µs and go to e. If TP is � 5 µs go to m. m. If TP is � 30 µs, the device is a reject.
n. After a delay of TD?, select the next output or address to be programmed.
o. Repeat steps 4.10d through 4.10k until all required addresses are programmed.
p. To verify the program keep VCC pin at VCCV. Apply VIL to CE 2. The programmed fuse will go to the low level and unblown fuse shall remain in the high level.
4.11 Programming procedures for circuit D. The programming characteristics on table IVD, and the following procedures shall be used for programming the device.
a. Connect the device in the electrical configuration for programming. The waveforms on figure 5D and the programming characteristics of table IVD shall apply to these procedures.
b. Select the word to be programmed by applying the appropriate voltages to the address pins as well as the required voltages to chip enable pins to select the device.
c. Apply the proper power, VCC = 6.5 V, GND = 0 V.
d. Verify that the bit to be programmed is in the "O" logic state.
e. Enable the chip for programming by application of the chip enable voltage, VP(CE1) = 21.0 V to CE 1
(pin 20). CE2 and CE3 should be left high.
f. Apply IOP programming current ramp to the output to be programmed. The other outputs shall be left open. Only one output may be programmed at a time. During the rise of the current ramp, the required current will be achieved to program the junction. As programming occurs a drop in voltage can be
sensed at the output of the device. Upon detection of VPS, the current shall be held for thap and then shut off.
g. Verify that the programmed bit is in the "1" logic state. Lower VP(CE1) to 0 V and read the output. Note: The PROM is supplied with fuses generating a low-level logic output. Programming a fuse will
cause the output to go to a high-level logic in the verify mode.
h. Lower VCC to 0 V. The power supply duty cycle shall be equal to or less than 50 percent.
i. If the bit verifies as not having been programmed at VCC = 6.5 V, then repeat the programming ramp sequence up to 15 times until the bit is programmed. If after 16 programming attempts, the bit does not program, then the device shall be considered a reject.
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