MIL-M-38510-210 Microcircuit, Digital, 16,384 Bit Schottky, Bipolar, Programmable Read-Only Memory Prom Monolithic SiliconThis specification covers the detail requirements for monolithic silicon, programmable read-only memory PROM microcircuits which employ thin film nichrome NiCr resistors, platinum-silicide, tungsten W, titanium-tungsten TiW or zapped vertical emitter as the fusible link or programming element. Two product assurance classes and a choice of case outlines and lead finishes are provided and are reflected in the complete part number. For this product, the requirements of MIL-M-38510 have been superseded by MIL-PRF-38535, see 6.4.

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MIL-M-38510/210F

i. If any bit does not verify as programmed, it shall be considered a programming reject.

4.9 Programming procedures for circuit C, device types 02 and 04; circuit K, device type 02. The programming characteristics of table IVC and the following procedures shall be used for programming device types 02 and 04.

a. Connect the device in the electrical configuration for programming. The waveforms on figure 5C, device types 02 and 04, and the programming characteristics of table IVC, device types 02 and 04, shall apply to these procedures.

b. Terminate all device outputs with a 10 kn resistor to VCC. Apply VIH to CE1.

c. Address the PROM with the binary address of the selected word to be programmed. Raise VCC to VCCP. d. After a tD delay (10 us), apply only one VOUT pulse to the output to be programmed. Program one

output at a time.

e. After a tD delay (10 us), pulse CE 1 input to logic "O" for a duration of tP.

f. After a tD delay (10 us), remove the VOUT pulse from the programmed output. (Programming a fuse will cause the output to go to a high-level logic in the verify mode.)

g. Other bits in the same word may be programmed sequentially while the VCC input is at the VCCP level by applying VOUT pulses to each output to be programmed allowing a delay to tD between pulses as shown on figure 5C.

h. Repeat 4.9b through 4.9g for all other bits to be programmed.

i. To verify programming, after tD (10 us) delay, lower VCC to VCCH and apply a logic "O" level to CE 1 input.

The programmed output should remain in the "1" state. Again, lower VCC to VCCL and verify that the

programmed output remains in the "1" state.

j. If any bit does not verify as programmed, it shall be considered a programming reject.

4.10 Programming procedures for circuit C, device type 05. The programming characteristics of table IVC, device type 05, and the following procedures shall be used for programming the device.

a. Connect the device in the electrical configuration for programming. The output pins shall be terminated with a 10 kn resistor to GND and bypass VCC to GND with a 0.01 uF capacitor. The waveforms on figure 5C, device type 05, and the programming characteristics of table IVC, device type 05, shall apply to these procedures.

b. Disable the device by applying VIH to CE 2 input and VIL to CE 1. The chip enable pins are TTL

compatible.

c. Apply VIL to all other pins.

d. Address the PROM with the binary address of the selected word to be programmed and reset TP = 5 us.

Address inputs are TTL compatible.

e. After a delay of TD1, raise the VCC pin to VCCP.

f. After a delay of TD2, raise the corresponding output pin to VOPF.

g. After a delay of TD3, lower CE 2 to VIL for a duration of TP and simultaneously lower the output to VIL

and wait TD4.