MIL-M-38510/103H
NOTES:
1. This circuit is designed especially to be used with a computer-controlled automatic tester, although it can also be implemented as a bench test setup. The test table for subgroups 9, 10, and 11 lists in detail the steps in a typical test sequence, which goes as follows:
a. Measure VIO: Device under test (DUT) is in a conventional servo loop (K3 and K4 energized) with output served to TTL logic threshold. (1.4 V on adapter pin 3). Measure VIO x 1000 adapter pin 8.
b. Null VIO: Release K3 and K4, apply voltage measured in step 1 to adapter pin 4. This is particularly easy to do on computer-controlled automatic test equipment.
c. Apply 5 mV overdrive (OD): The overdrive is developed at the inverting input of the device under test (DUT) via a 1000:1 divider from adapter pin 5.
d. Apply initial 100 mV: Close K1, apply 2 mA at adapter pin 6. Since Q1 is off, this current flows through
Schottky diode D1 and the 50 n source resistor, giving 100 mV. If a current source is not available,
15 V at pin 6 will give about 2 mA current.
e. Measure tRLHC: Pull adapter pin 7 low. U1A output goes high, starting the timer via U1B and turning on
Q1, which turns off D1. The 100 mV drive disappears abruptly, leaving just the 5 mV overdrive.
After the response time, the device under test (DUT) output crosses TTL logic threshold and stops the timer via U1B. On a bench setup, the pulse at 1UB output can be measured with a scope.
f. Measure tRHLC: Reset pin 7, change pin 5 from -5 V to +5 V, open K1, close K2, pull pin 7 low, measure pulse width at U1B output.
2. The following delay times are of possible concern in the LM119 (device types 06 and 07) response time test circuit:
a. U1A: This device merely inverts and squares up the start signal from the tester. Its gate delay does not affect the tests.
b. Q1: This is the major uncompensated delay, since the timer starts when Q1 base goes high, not when Q1 collector goes low. This delay is minimized by using a fast switching transistor with an R-C speedup
network driving the base. Measured Q1 delays are well under 10 ns.
c. D1 and D2: These Schottky devices have negligible switching times ( < 1 ns).
d. U1B: The gate delays here are not important as long as the delays from the two inputs are well matched. (Matched delays merely offset the output pulse in time.) To minimize gate delay effects even further,
we use one of the "fast" series 74F86 gates; with delays around 5 ns from each input, the mismatch should be no more than 1 or 2 ns.
e. Q2: This driver is required only if the time measurement systems has a 50 n input. Since it operates as an emitter follower rather than a saturating switch, there are no delays associated with it.
3. As required to prevent oscillations. Also, proper wiring procedures shall be followed to prevent oscillations.
Loop response and settling time shall be consistent with test rate such that any value has settled to within
5 percent of its final value before value is measured. Suggested values shown may not ensure loop stability for all layouts. Actual compensation used shall be approved by preparing activity prior to use.
4. All resistor tolerances are ±1 percent and all capacitor tolerances are ±10 percent.
5. CL includes scope, probe, and jig capacitance.
FIGURE 6. Response time test circuit for device types 06 and 07 - continued.
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