MIL-M-38510-555 Microcircuits, Digital, Cmos, Remote Terminal Interface, Monolithic SiliconThis specification covers the detail requirements for monolithic silicon, CMOS, remote terminal interface RTI microcircuits. One product assurance class class B and a choice of case outlines, and lead finishes are provided and are reflected in the complete Part or Identifying Number PIN. For this product, the requirements of MIL-M-38510 have been superseded by MIL-PRF-38535 see 6.3.

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MIL-M-38510/555B

10. SCOPE

APPENDIX

DESIGN LIMIT TIMING PARAMETERS

10.1 Scope. This appendix contains supplementary timing parameters with associated diagrams for clarification that are to be used as design limits. Due to testing limitations, these parameters cannot be tested, many of these timings are such that it is impractical to do so. This appendix is a mandatory part of the specification and the information contained herein is intended for compliance.

20. APPLICABLE DOCUMENTS. This section is not applicable to this appendix.

30. DESIGN LIMIT TIMING PARAMETERS 1/

Symbol	Parameter		Min	Max	Units	Figure	Notes
tPLH39 tPHL39	Command word mid-parity bit to CH A/B valid		2.58	2.66	µs	14
tPHL40	Comm	and word mid-parity bit to COMSTR(L) and RCV(L) or L)	3.58	3.67	µs	14, 17, 19
tPHL40	XMIT(	and word mid-parity bit to COMSTR(L) and RCV(L) or L)	3.58	3.67	µs	14, 17, 19
tWL41	COMSTR low pulse width		499	502	ns	14
tPHL42	BRDCST, MC/SA, MCSA, ADDR OUT valid before COMSTR(L) (set-up)		430		ns	14	2/
tPHL43	COMSTR(L) to MES ERR		745	750	ns	14	3/
tPLH44	Received data word mid-parity bit to DMARQ(H)		3.58	3.68	µs	15, 16
t00LH45	ADDR OUT valid before DMARQ(H)		0.9		µs	15
tPHL46	1553B response time BIPHASE to BIPHASE OUT		8.80	9.37	µs	16, 17, 19	4/
tPLH47	STATUS(H), RCV(H) before BIPHASE OUT(H)		1.24	1.25	µs	16, 17, 19
tWH48	STATUS high pulse width		4.48	4.98	µs	16, 17, 19
tPLH49	Transmit command mid-parity bit to DMARQ(H) for first word to be transmitted		12.05	12.16	µs	17
tPLH50	DMARQ(H) lead time before mid-data sync of data word to be transmitted		17.15	17.18	µs	18	5/
tPLH51	DMARQ(H) to next DMARQ(H) during transmit			19.92	µs	18	5/
tPLH52	XMIT(H) after last DMARQ(H)		460	500	ns	18
tWL53	XMIT low pulse width for mode codes without data words		1.0		µs	19
tPLH54	Illegal mode command mid-parity bit to MES ERR(H)		6.57	6.68	µs	19	6/
tPLH55	Data word mid-parity bit to MES ERR(H) timeout for missing data words during receive		23.50	23.63	µs	20
tPLH56	Receive command mid-parity bit to MES ERR(H) timeout for no response from the transmitter during RT to RT		55.4	55.5	µs	21	7/

1/ These additional timing parameters are meant to supplement those given in table I. These timing parameters were derived from logic simulations (fast and slow conditions) and are not tested or guaranteed.

2/ The ADDR OUT will contain the 11-bit command word.

3/ MES ERR was high from a previous command. This is part of the status word reset requirements given in MIL-STD-1553. MES ERR will remain high if the current command is a transmit status word or a transmit last command mode code.

4/ In accordance with MIL-STD-1553.

5/ This is true only if DMARQ is acknowledged (via MEMCK by the host within the time constraints given in table I. If these time constraints are exceeded, the RTI will be forced to introduce gaps between the transmitted data words which will be a violation of MIL-STD-1553 with respect to data contiguity.

6/ This refers to mode codes internally decoded within the RTI as illegal.

7/ See notice 2 of MIL-STD-1553.