MIL-M-38510/555B
6.5.3 Interface architecture.
6.5.3.1 Decoders. The RTI contains two separate free-running decoders to insure that all redundancy requirements of
MIL-STD-1553B are met. See figure 2. Each decoder receives, decodes, and verifies biphase Manchester II data. Proper frequency and edge skew are also verified.
6.5.3.2 Command recognition logic. The command recognition logic monitors the output of both decoders at all times. Recognition of a valid commend causes a reset of present interface activity followed by execution of the command. This meets the requirement for superseding valid commands.
6.5.3.3 Encoder. The encoder receives serial data from the data transfer logic, converts it to Manchester II form with proper sync and parity, and passes it to the output and self-test logic.
6.5.3.4 Data transfer logic. The data transfer logic provides double buffered 16-bit parallel-to-serial and serial-to- parallel conversion during reception and transmission of data.
6.5.3.5 Memory address control. The memory address control logic controls the output of the three-state address lines during memory access. In DMA system implementations, the memory address control provides interface- generated addresses. In transparent dual-port memory implementations, the memory address control logic provides either interface-generated or host system addressing.
6.5.3.6 Control and error logic. The control and error logic performs the following four major functions:
a. Interface control for proper processing of MIL-STD-1553 commands. b. Error checking for both MIL-STD-1553 data and RTI operation.
c. Memory control (DMA or transparent) for proper data transfer. d. Operational status and control handshaking with host system.
6.5.3.7 Output multiplexing and self testing logic. This logic directs the output of the encoder to one of four places:
a. Channel A outputs. b. Channel B outputs.
c. Channel A decoders during self-test. d. Channel B decoders during self-test.
6.5.3.8 Clock and reset logic. The RTI requires a 12 MHz input clock to operate properly. It provides a 2 MHz output for the system designer's use. The device provides a hardware reset pin as well as software-generated reset.
6.5.3.9 Timer logic. The RTI has a buit-in 730 microsecond timer that is activated when the encoder is about to transmit. The timer is reset upon receipt of a valid command or a master reset.
6.5.4 Initializing the RTI.
a. During power-up the master reset (MRST) pin must be asserted to put the RTI in a known state. After a reset, the control register is cleared which means that both communication channels A and B are disabled. Therefore, a control register write (see 6.5.9) must be performed to at least enable the communication channels and allow the RTI to start receiving commands.
b. A software reset is also available so that the host can selectively initialize the RTI. This is accomplished by simultaneously asserting CS and CNTRL, RD/WR = 0, and ADDR IN (0) = 1.
6.5.5 Receive operation.
a. The receive operation is illustrated via the following example (see figure 11). Detailed timing parameters are given in figure 6, and the appendix (figures 14, 15, and 16).
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