MIL-M-38510-555 Microcircuits, Digital, Cmos, Remote Terminal Interface, Monolithic SiliconThis specification covers the detail requirements for monolithic silicon, CMOS, remote terminal interface RTI microcircuits. One product assurance class class B and a choice of case outlines, and lead finishes are provided and are reflected in the complete Part or Identifying Number PIN. For this product, the requirements of MIL-M-38510 have been superseded by MIL-PRF-38535 see 6.3.

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MIL-M-38510/555B

d. When the RTI is placed in a self-test condition, it will immediately begin transmitting the status word. The state of the status word is not altered when the RTI is placed in self-test. Since the status word and the command word sync pulses are identical, the decoder will interpret the status word being fed back to it as a command word.

e. Any error condition during self-test will cause a status word transmission in order to prevent the

RTI from hanging up.

f. The actual self-test should be controlled by the host; the RTI has no predefined self-test routine.

The status word from the encoder being fed back to the decoder can be modified by control register writes. The self-test can be monitored via the system and/or last command registers.

Only transmit commands can be used during self-test to check for data transfers between RTI and memory. This is because a receive command (which was a status word from the encoder) will

effectively cancel the transmission of the associated data words.

g. There are two ways to get out of self-test. The first is via a master reset. The second is to negate the EXT TEST pin or the self-test bit in the control register. This does not actually stop the self-test but causes the encoder-to-decoder link to be severed on the next valid command generated by the self-test.

TABLE VI. Last command register.

Bit 0	Last command word bit 0.
Bit 1	Last command word bit 1.
Bit 2	Last command word bit 2.
Bit 3	Last command word bit 3.
Bit 4	Last command word bit 4.
Bit 5	Last command word bit 5.
Bit 6	Last command word bit 6.
Bit 7	Last command word bit 7.
Bit 8	Last command word bit 8.
Bit 9	Last command word bit 9.
Bit 10	Last command word bit 10.
*Bit 11	Busy. A logic 1 indicates that the host has enabled the busy bit of the control register and status word.
*Bit 12	Self-test. A logic 1 indicates that the RTI is currently in either the internal or external self-test mode.
*Bit 13	Terminal flag enabled. A logic 1 indicates that the RTI has not received an "inhibit terminal flag bit" mode code and the host is able to set the terminal flag bit of the status register. A logic 0 indicates that the host is disabled from setting the terminal flag bit of the status word. In this situation, the host can only set the status word terminal flag by either receiving an "override inhibit terminal flag bit" mode code of through a master reset.
*Bit 14	Channel A or B. A logic 1 indicates that the most recent command arrived on channel A; a logic 0 indicates that it arrived on channel B.
Bit 15	Illegal command. A logic 1 indicates that the last command received was either decoded internally or externally as an illegal command.

* These bits are also available in the system register.