MIL-M-3851O/555B
b. A receive command word and its associated data words (five in this example) are sent contiguously by bus controller (BC) to the RTI's biphase inputs, as follows (hexadecimal notation). See figure 12.
A8C5 TA = 1O1O1, T/R = O, SA = OO11O, WC = OO1O1
OOOA First data word OOOB Second data word OOOC Third data word OOOD Fourth data word OOOE Fifth data word
c. After command word validation, the command strobe, (COMSTR) line is pulsed low and the RTI's receive output (RCV) will also go low to indicate to the host that a receive operation is in effect. The subaddress will also be valid in the mode code/subaddress MCSA lines. The command word is stored internally in the last command register.
d. After validating the first incoming data word, the RTI will assert the DMA request (DMARQ) line to notify the host that it has to do a memory transfer.
e. The host responds to the DMA request by asserting the RTI's memory clock (MEMCK) input. This action causes the RTI's memory access control lines RAM chip-select (RCS) and RAM read/write (RRD/RWR) to go low. The RTI will also put the data word in the data bus (DT bus). Memory addresses (ADDR OUT bus) are generated automatically by the RTI (see item 6.5.5j).
f. The host will then negate MEMCK after it has determined that the memory devices have read in the data word from the RTI's DT bus. This action causes the RTI's memory access control lines (RCS and RRD/RWR) to go high and the DT bus to be three-stated (high impedance state).
g. The sequence above will be repeated until all data words are received by the RTI. After the last data word is processed, the status word is transmitted to the bus controller via the RTI's biphase outputs. The RTI's status (STATUS) line will also go high to indicate to the host that the status word is being transmitted.
h. The RTI is capable of processing the maximum word count (32) and all subaddresses (O1 through
1E).
i. If the busy bit of the status register is set, all DMARQ assertions are suppressed although a status word will be transmitted.
j. During this receive operation, the contents of the address (ADO) and data (DT) busses will be as follows:
address |
data |
comments |
OC4 |
OOOA |
first data word |
OC3 |
OOOB |
second data word |
OC2 |
OOOC |
third data word |
OC1 |
OOOD |
fourth data word |
OCO |
OOOE |
fifth data word |
k. Notice that the addresses generated by the RTI are derived directly from the least 11 bits of the command word. The addresses will always count down to zero. For example, if 32 words were received, the first address will be ODF (OOO11O11111).
l. With an 11-bit address field, the RTI is capable of accessing 2O48 memory locations. Since the T/R bit of command word is the most significant bit of this address field, the 2K memory space is divided into transmit and receive blocks of 1K each. Therefore, for data "wrap-around" applications (transmitting data that was previously received), ADDR OUT 1O must be tied high or low.
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