MIL-M-38510-555 Microcircuits, Digital, Cmos, Remote Terminal Interface, Monolithic SiliconThis specification covers the detail requirements for monolithic silicon, CMOS, remote terminal interface RTI microcircuits. One product assurance class class B and a choice of case outlines, and lead finishes are provided and are reflected in the complete Part or Identifying Number PIN. For this product, the requirements of MIL-M-38510 have been superseded by MIL-PRF-38535 see 6.3.

Pages 1 - 2 - 3 - 4 - 5 - 6 - 7 - 8 - 9 - 10 - 11 - 12 - 13 - 14 - 15 - 16 - 17 - 18 - 19 - 20 - 21 - 22 - 23 - 24 - 25 - 26 - 27 - 28 - 29 - 30 - 31 - 32 - 33 - 34 - 35 - 36 - 37 - 38 - 39 - 40 - 41 - 42 - 43 - 44

Bit 0

Channel A enable.  A logic 1 will enable channel A.

Bit 1

Channel B enable.  A logic 1 will enable channel B.

Bit 2

Terminal flag.  A logic 1 will cause the terminal flag bit of the status word to be asserted.  The terminal flag bit of the status word will actually be asserted if the RTI had not received an "inhibit terminal flag" mode

command.

Bit 3

System busy.  A logic 1 will assert the busy bit of the status register and will suppress all OMA requests

by the RTI.

Bit 4

Subsystem flag.  A logic 1 will assert the subsystem flag of the status register.

Bit 5

Internal test channel select.  A logic 1 selects channel A; a logic 0 selects channel B.

Bit 6

Internal test.  A logic 1 places the RTI into self-test mode.

Bit 7

Service request.  A logic 1 will assert the service request bit of the status register.

Bit 8

•

•

Oon't cares.

•

Bit 15

Bit 0

Mode code/subaddress bit 0.

Bit 1

Mode code/subaddress bit 1.

Bit 2

Mode code/subaddress bit 2.

Bit 3

Mode code/subaddress bit 3.

Bit 4

Mode code/subaddress bit 4.

Bit 5

Mode code/subaddress. A logic 1 indicates the last command was a normal transmit or receive command

(non-mode) and that bits 4 through 0 above comprise the subaddress field of that command.  A logic 0 indicates that the last command was a mode command and that bits 4 through 0 above comprise the mode code field of that command.

*Bit 6

Channel A or B.  A logic 1 indicates that the most recent command arrived on channel A; a logic 0 indicates that it arrived on channel B.

Bit 7

Channel B enabled.  A logic 1 indicates that channel B is enabled for both transmission and reception.

Bit 8

Channel A enabled.  A logic 1 indicates that channel A is enabled for both transmission and reception.

*Bit 9

Terminal flag enabled.  A logic 1 indicates that the RTI has not received an "inhibit terminal flag bit" mode

code and the host is able to set the terminal flag bit of the status register.  A logic 0 indicates that the host is disabled from setting the terminal flag bit of the status word.  In this situation, the host can only set the status word terminal flag by either receiving an "override inhibit flag bit" mode code of through a master reset.

*Bit 10

Busy.  A logic 1 indicates that the host has enabled the busy bit of the control register and status word.

*Bit 11

Self-test.  A logic 1 indicates that the RTI is currently in either the internal of external self-test mode.

Bit 12

Bad terminal address parity.  A logic 1 indicates that the RTI has detected a parity error on the terminal address.  It also indicates that the RTI has disabled the communication channels and is unable to receive

commands.

Bit 13

Message error latch.  A logic 1 indicates that at some time a message error condition has occurred.  This bit will not return to a logic 0 until the system register has been read.

Bit 14

Valid message latch.  A logic 1 indicates that at some time a valid message has been received. This bit will not return to a logic 0 until the system register has been read.

Bit 15

Terminal active.  A logic 1 indicates that the RTI is currently processing a transmit or receive instruction.

This bit is the logical NANO of the RTI's external XMT and RCV pins.