MIL-M-38510-555 Microcircuits, Digital, Cmos, Remote Terminal Interface, Monolithic SiliconThis specification covers the detail requirements for monolithic silicon, CMOS, remote terminal interface RTI microcircuits. One product assurance class class B and a choice of case outlines, and lead finishes are provided and are reflected in the complete Part or Identifying Number PIN. For this product, the requirements of MIL-M-38510 have been superseded by MIL-PRF-38535 see 6.3.

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Input leakage for inputs without pull-down

resistors

IIHW

VIN  = 5.5 V

All

1,2,3

10

µA 2/

Input leakage current for

IILP

VSS  = GND

All

1,2,3

-2.75

-0.11

mA 2/

inputs with pull-up

VIN  = GND (PU)

resistors

Input leakage current for

IIHP

VSS  = GND

All

1,2,3

0.11

2.75

mA 2/

inputs with pull-down

VIN  = VDD  (PD)

resistors

Output leakage current

(three-state)

ILOZ(H)

VADDROUT  = 5.5 V VADOEN  = VOH

All

1,2,3

-10

10

µA

Output leakage current

(three-state)

ILOZ(L)

VADDROUT  = 0.0 V VADOEN  = VOH

All

1,2,3

-10

10

µA

Output leakage current

(bi-direct)

ILB(H)

VDT  = 5.5 V VMRST  = VOL

All

1,2,3

-10

10

µA

Output leakage current

(bi-direct)

ILB(L)

VDT  = 0.0 V VMRST  = VOL

All

1,2,3

-10

10

µA

Low level output voltage

VOL

IOL = 4.0 mA

All

1,2,3

0.4

V

High level output voltage

VOH

IOH  = -0.4 mA

All

1,2,3

2.4

V

Low level input voltage

VIL

All

1,2,3

0.8

V

3/

Input clamp voltage

(positive)  3/

VIC+

VDD  = GND; IIN = 1 mA

TC = +25°C

All

1

0.4

1.8

V

Input clamp voltage

(negative)  3/

VIC-

VDD  = OPEN;

IIN  = -1 mA

All

1

-0.4

-1.8

V

TC = +25°C

Input capacitance 4/

CI

VI  = 0.0 V; F = 1 MHz

All

4

10

pF 5/

TC = +25°C

Output capacitance 4/

CO

VO  = 0.0 V; F = 1 MHz

All

4

20

pF 5/

TC = +25°C

Bidirect capacitance 4/

CB

VO  = 0.0 V; F = 1 MHz

All

4

25

pF 5/

TC = +25°C

Quiescent current 6/

IDD

All

1,2,3

50

mA

CS(L) to RCS(L)

tPHL1

See figures 4 and 5

All

9,10,11

48

ns

CS(H) to RCS(H)

tPLH2

All

9,10,11

40

ns

RD/WR(L) to RRD/RWR(L)

tPHL3

All

9,10,11

45

ns

RD/WR(H) to RRD/RWR(H)

tPLH4

All

9,10,11

35

ns

CS(L) to ADDR OUT(H)

tPLH5

All

9,10,11

6

52

ns

CS(L) to ADDR OUT(L)

tPHL5

All

9,10,11

6

52

ns

8/