MIL-M-38510/555B
For example, although the RTI will accept and respond to a "reset remote terminal" mode command, it will not perform a reset operation. It will be up to the host to interpret the mode command and take appropriate action.
f. The data word associated with the following mode commands are not defined or interpreted by the RTI: (1) Transmit vector word.
(2) Synchronize with data word.
(3) Transmit BIT (built-in-test) word.
For example, although the RTI will accept and respond to a "synchronize with data word" and store the data word in memory, it is up to the host to interpret the contents of this data word. Likewise, the RTI will retrieve a word from memory during a "transmit BIT word" command. However, it is up to the host to define the contents of this word.
6.5.8 Broadcast commands.
a. The RTI will accept all valid and legal mode and nonmode broadcast commands in all message formats. Upon receipt of a broadcast command, the RTI will assert its broadcast (BRDCST) line.
b. In order for the RTI to process broadcast commands, its broadcast enable (BCEN) input must be low.
6.5.9 Control register writes.
a. The RTI is controlled via an 8-bit control register which is defined in table IV. A control register write is performed by simultaneously asserting the CTRL and CS signals, RD/WR = 0, and ADDR IN (0) = 0 (least significant bit of the address input bus). Detailed timing parameters for a control register write are given on figure 8.
b. A control register write may be performed anytime; however, toggling status word bits are subject to the following conditions:
c. A control register write can be done to assert a status word bit (service request, subsystem flag, busy, or terminal flag). However, note that if a control register write is performed on or before the status (STATUS) line goes high, the transmitted status word will reflect the updated contents of the control register. If the control register is done after STATUS goes low, the transmitted status word will not reflect the updated control register.
d. To remove or negate a status word bit, the control register write must be completed 50 ns before the rising edge of the command strobe (COMSTR) pulse in order for the current status word to be updated. Otherwise, the status word will be updated only on the receipt of the next command word.
e. Under certain conditions, the external terminal address lines can only be enabled by doing a control register write.
6.5.10 System register access.
a. The status of the RTI can be obtained from a 16-bit system register which is defined in table V. A system register read is performed by asserting CTRL and CS at the same time (RD/WR = 1) and placing the least significant bit of the address input bus (ADDR IN) at a logic 0. Detailed timing parameters for a system register read are given on figure 9.
b. Although a system register read can be done anytime, it is recommended that it be done after STATUS goes to a logic 1. The valid message latch is set at this time indicating that a valid message has been received. After the system register read, the valid message latch is reset.
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