MIL-M-38510-555 Microcircuits, Digital, Cmos, Remote Terminal Interface, Monolithic SiliconThis specification covers the detail requirements for monolithic silicon, CMOS, remote terminal interface RTI microcircuits. One product assurance class class B and a choice of case outlines, and lead finishes are provided and are reflected in the complete Part or Identifying Number PIN. For this product, the requirements of MIL-M-38510 have been superseded by MIL-PRF-38535 see 6.3.

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MIL-M-38510/5558

6.5.14    Transparent memory access.

a.        A host performs a "transparent" memory access when it does a memory transfer to or from a memory device whose address and control lines are connected to the RTI.  The host does this by asserting the CS and RD/WR pins and placing an 11-bit address on the RTI's address input pins. The signal CTRL must remain at a logic 1 at all times during transparent memory access to prevent the RTI from performing a control register write, a system register read, a last command register read, or a software master reset.

b.        The CS pin when at a logic 0 will prevent the RTI itself from doing a memory access; this means that the data bus will remain at high impedance and the address outputs and RAM read/write (RRD/RWR) will reflect the state of the address inputs and RD/WR lines respectively.

c.        The RTI will still be able to assert the DMARQ line while CS is at a logic 0 although MEMCK transitions will not be recognized.  This implies that the RTI can still process incoming commands while it is being used by the host.  Note that the RTI recognizes MEMCK transitions only; therefore, if MEMCK is asserted (in response to DMARQ) while CS is at logic 0, it will have to be negated

and reasserted when CS goes high.

6.5.15    Terminal fail-safe operation.

a.        The RTI has a built in counter that will time out in 730 µs.  Detailed timing parameters are shown on figure 11.  This timer is activated whenever the encoder is enabled and is about to transmit information on the biphase outputs.  This is indicated by the signal TIMERON going to a logic 0.

b.        When the RTI receives a valid command, it will reset the timer during COMSTR time and return signal TIMERON back to a logic 1.  The timer will also reset when it has reached its timeout period or when the RTI is reset.

c.        During external test, the timer will not recognize the COMSTR signal and will be allowed to time out so that the host will be able to test its external fail-safe hardware.

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