MIL-M-38510-555 Microcircuits, Digital, Cmos, Remote Terminal Interface, Monolithic SiliconThis specification covers the detail requirements for monolithic silicon, CMOS, remote terminal interface RTI microcircuits. One product assurance class class B and a choice of case outlines, and lead finishes are provided and are reflected in the complete Part or Identifying Number PIN. For this product, the requirements of MIL-M-38510 have been superseded by MIL-PRF-38535 see 6.3.

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MIL-M-38510/555B

TABLE I. Electrical performance characteristics - Continued.

Test		Symbol	Conditions 1/ -55qC ≤ TC ≤ +125qC unless otherwise specified	Device type	Group A subgroup	Limits		Unit
Test		Symbol		Device type	Group A subgroup	Min	Max	Unit
Input DATA valid after RCS(H) (hold)		tHLH26	See figures 4 and 7	All	9,10,11	5		ns
DMARQ(H) to MEMCK (H) response, xmit		tOILH27	See figures 4 and 7	All	9,10,11		18.3	µs
Input DATA valid (setup) before control write (H)		tSLH28 14/	See figures 4 and 8	All	9,10,11	20		ns
Input DATA valid (hold) after control write (H)		tHLH29 14/		All	9,10,11	25		ns
ADDR IN 0 = 0 (setup time before control write (L) so software reset is not recognized		tSHL30 14/		All	9,10,11	20		ns
ADDR IN 0 = 0 (hold time after control write (H) so software reset is not recognized		tHLH31 14/		All	9,10,11	20		ns
(CTRL + CS) (L) to DATA bus (H) while ADDR IN 0 = 1 or 0		tPZH32	See figures 4 and 9	All	9,10,11		132	ns
(CTRL + CS) (L) to DATA bus (L) while ADDR IN 0 = 1 or 0		tPZL32		All	9,10,11		132	ns
ADDR IN 0 (valid) to DATA bus (H) while (CTRL + CS) = 0		tPLH33		All	9,10,11		70	ns
ADDR IN 0 (valid) to DATA bus (L) while (CTRL + CS) = 0		tPHL33		All	9,10,11		70	ns
(CTRL + CS) (H) to DATA(L) Bus Hi-Z 9/		tPLZ34		All	9,10,11		101	ns
(CTRL + CS) (H) to DATA(H) Bus Hi-Z 9/		tPHZ34		All	9,10,11		101	ns
Status (H) before TIMERON (L) 9/		tOOHL35	See figures 4 and10	All	9,10,11	4	31	ns
	N (L) before first iphase n 9/	tOOLH36		All	9,10,11	1.2		µs
TIMERO output b transitio	N (L) before first iphase n 9/	tOOLH36		All	9,10,11	1.2		µs
TIMERON low pulse width (during time out) 9/		tPWL37		All	9,10,11		730	µs 15/
COMSTR(L) to TIMERON (H) (reset) 9/		tOOLH38			9,10,11		31	ns

1/ Output levels are tested in static (dc) state and are specified over the voltage range of VDD.

VDD = 5.0 V ± 10 percent, unless otherwise specified.

2/ Refer to figure 1 for identification of inputs with pull-up or pull-down resistors.

3/ These tests are performed as a go/no-go tests.

4/ See 4.4.1c.