MIL-M-38510-555 Microcircuits, Digital, Cmos, Remote Terminal Interface, Monolithic SiliconThis specification covers the detail requirements for monolithic silicon, CMOS, remote terminal interface RTI microcircuits. One product assurance class class B and a choice of case outlines, and lead finishes are provided and are reflected in the complete Part or Identifying Number PIN. For this product, the requirements of MIL-M-38510 have been superseded by MIL-PRF-38535 see 6.3.

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DATA I/O 0-15

16-bit bidirectional data port for all data transfer between the RTI and host system.

ADDR IN 0-10

11-bit host system address input if it is in transparent memory mode.  Not used in DMA configuration.

ADDR OUT 0-10

11-bit three-state address output.  Contains processor or RTI-generated address

(CS selects processor address).

ADOEN

Address out enable.  Causes ADDR OUT lines to be active when low, high impedance when high.

CS

Processor chip select.  Active low input for host system access of transparent memory or the RTI

registers.

RD/WR

Processor read/write.  High input in conjunction with CS and for host system read of transparent memory, system register or last command read function.  Low input in conjunction with CS for host system write to transparent memory or control register.

CTRL

Control select.  Active low in conjunction with CS and RD/WR for host system access to the RTI registers.  This signal is also used to latch terminal address input lines (if TALEN/PARITY = 1) and to generate programmable reset.

MEMCK

Memory clock (DMA acknowledge).  Active low synchronizing input used to generate reads or writes to

memory.

DMARQ

Direct memory access request.  Active high output requests RTI access of memory.

RCS

Ram chip select.  Active low output enables memory access.

RRD/RWR

RAM read/write.  High output enables memory read, low output enables memory write (in conjunction

with RCS).  Quiescent state = high.

TIMERON

Active low pulse of 730 microseconds maximum duration started by the rising edge of STATUS which is used with external logic to provide a less than 800 microseconds fail-safe timer.  This pulse is reset

when COMSTR goes low or during a master reset.  During external self test, the timer will not recognize the COMSTR signal and will be allowed to timeout in order to test the external fail-safe hardware.

VDD, GND

Power supply inputs.

BCEN

Broadcast enable.  Active low input enables broadcast commands.

COMSTR

Command strobe.  An active low output of 500 nanoseconds duration identifying receipt of a valid command and that all the RTI indicators (MC/SA, MCSA 0-4, XMIT, RCV, BRDCST) are valid.

2 MHz

2 megahertz free running clock output.

MRST

Master reset.  Active low signal that initializes all internal nodes, must be followed by host system write

to control register to enable the communication channels.

12 MHz

2 megahertz clock input.

TALEN/PARITY

Terminal address latch enable/party.  The function of the TALEN/PARITY signal is dependant upon the state of the external test (EXTST, pin 29) and external test channel select (EXT TST CH SEL A/B,

pin 31) signals.  In all cases, if TALEN/PARITY is low, the terminal address will be strobed into the TA

lines (TA0-TA4); otherwise, the terminal address can only be loaded via a control register write.

EXT TEST

EXT TST CH SEK A/B

Function of TALEN/PARITY.

0

0

External terminal address latch control only. Terminal address parity is not checked.

0

1

Odd parity bit for the terminal address and external terminal address

latch control.  Terminal address parity is checked.

1

0

External terminal address latch control only. Terminal address parity is not checked.

1

1

External terminal address latch control only. Terminal address parity is checked.