MIL-M-38510/555B
6.5.11 Last command register access.
a. The last command register of the RTI is defined in table VI. A last command register read is performed by asserting CTRL and CS at the same time (RD/WR = 1) and placing the least significant bit of the address input bus (ADDR IN) at logic 1. Detailed timing parameters for a last command register read are identical to a system register read given in figure 9.
b. A last command register read can be done anytime. However, the last command register is updated during COMSTR time except when the RTI receives a "transmit last command."
6.5.12 External illegal command decoding.
a. As mentioned in 6.5.5c, the host has the option of asserting the ILL COMM line if it cannot support a valid command it has received. On receipt of an illegal command, the RTI will set the message error bit in the status word, set the message error output (MES ERR), and set the message error latch in the system register.
The following RTI outputs may be used to externally decode an illegal command; mode code of subaddress indicator (MC/SA), mode code, or subaddress bus (MCSA 0-4), the transmit indicator (XMIT), the receive indicator (RCV), and the broadcast indicator (BRDCST) and command strobe (COMSTR).
b. For proper external illegal command decoding; the following timing guidelines should be followed: (1) The ILL COMM line must be asserted within 3.3 µs after STATUS goes to a logic 1 if the host
intends to respond with the ME bit of the status word at a logic 1, except when the illegal
command is mode code 2, 4, 5, 6, 7, or 18, in which case the ILL COMM line must be valid
178 ns after COMSTR goes to a logic 1.
(2) The minimum pulse width for the ILL COMM signal is 1 µs.
(3) For illegal receive commands, the ILL COMM line must be asserted within 18.2 µs after the COMSTR pulse in order for DMA requests to be suppressed. In addition, the ILL COMM line must be at a logic 1 throughout the reception of the message until STATUS is asserted. This does not apply to illegal transmit commands since the status word is transmitted first provided conditions 6.5.12b(1) and 6.5.12b(2) above are met.
(4) The above timing conditions also apply when the host externally decodes an illegal broadcast command. However, caution must be exercised since the status word transmission is suppressed and the STATUS line stays at a logic 0 giving no external hardware indication that the message has been completely received. The host will have to continually monitor the
valid message bit of the system register to obtain this information. The host must remove the illegal command condition so that the next command will not be falsely decoded as illegal.
6.5.13 Self-test.
a. The RTI can be placed in a self-test condition by asserting the EXT TEST pin or writing a logic 1 into bit 7 of the control register. A self-test condition will cause the encoder output to be fed back to decoder A or B depending on the status of the EXT TST CH SEL (external test channel select) pin or bit 6 of control register.
b. When external self-test is enabled, any transmission by the RTI will appear on its biphase outputs.
During an internal self-test, the biphase outputs are disabled.
c. During self-test, the biphase input channels are disabled. Therefore, the RTI will not be able to receive commands. It is not necessary to enable the channels in the control register to perform a self-test.
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