MIL-M-38510-53 Microcircuits, Digital, Cmos, Complimentary Pair Plus Inverter, And-Or-Select Exclusive Or Gates, Expandable 8-Input Gate Monolithic SiliconThis specification covers the detail requirements for monolithic silicon, CMOS, logic microcircuits. Two product assurance classes and a choice of case outlines, lead finishes, and radiation hardness assurance RHA are provided and are reflected in the complete Part or Identifying Number PIN. For this product, the requirements of MIL-M-38510 have been superseded by MIL-PRF-38535 see 6.3.

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MIL-M-38510/53F

4. VERIFICATION

4.1 Sampling and inspection. Sampling and inspection procedures shall be in accordance with MIL-PRF-38535 or as modified in the device manufacturer's Quality Management (QM) plan. The modification in the QM plan shall not affect the form, fit, or function as described herein.

4.2 Screening. Screening shall be in accordance with MIL-PRF-38535 and shall be conducted on all devices prior to qualification and conformance inspection. The following additional criteria shall apply:

a. The burn-in test duration, test condition, and test temperature, or approved alternatives shall be as specified in the device manufacturer's QM plan in accordance with MIL-PRF-38535. The burn-in test circuit shall be maintained under document control by the device manufacturer's Technology Review Board (TRB) in accordance with MIL-PRF-38535 and shall be made available to the acquiring or preparing activity upon request. The test circuit shall specify the inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in test method 1015 of MIL-STD-883.

b. Delete the sequence specified as interim (pre-burn-in) electrical parameters through interim (post-burn-in)

electrical parameters of table IA of MIL-PRF-38535 and substitute lines 1 through 7 of table II herein.

c. Burn-in (method 1015 of MIL-STD-883).

(1) Unless otherwise specified in the manufacturers QM plan for static tests (test condition A), case temperature (TC) shall be +125°C minimum. Test duration for each static test shall be 24 hours minimum for class S devices and in accordance with table I of method 1015 for class B devices.

i. For static burn-in I, all inputs shall be connected to 0.0 V. ii. For static burn-in II, all inputs shall be connected to VDD.

iii. Except for VDD and VSS, the terminal shall be connected through resistors whose value is 2

kn to 47 kn. The actual measured value of the resistor selected shall not exceed ±20% of its branded value due to use, heat or age.

iv. Output may be open or connected to VDD/2. v. For device types 01 and 51:

(a) Connect pins 2, 11, and 14 together. (b) Connect pins 4, 7, and 9 together.

vi. VDD = 12.5 V minimum and 15 V maximum for device types 01, 02, 03, and 04.

VDD = 15 V minimum and 18 V maximum for device types 51, 52, 53, and 54.

VDD/2 = VDD/2 ± 1.0 V for all devices. VSS = 0.0 V.

(2) Unless otherwise specified in the manufacturers QM plan for dynamic test (test condition D), case temperature shall be +125°C minimum. Test duration shall be in accordance with table I of method 1015.

i. Except for VDD and VSS, the terminals shall be connected through resistors whose value is

2 kn to 47 kn. The actual measured value of the resistor selected shall not exceed ±20%

of its branded value due to use, heat or age.

ii. Input signal requirements: Square wave, 50% duty cycle; 25 kHz < PRR < 1 MHz; tTLH and tTHL < 1 µs. Voltage level: Minimum = VSS - 0.5 V, +10% VDD;

maximum = VDD + 0.5 V, -10% VDD.