MIL-M-38510-53 Microcircuits, Digital, Cmos, Complimentary Pair Plus Inverter, And-Or-Select Exclusive Or Gates, Expandable 8-Input Gate Monolithic SiliconThis specification covers the detail requirements for monolithic silicon, CMOS, logic microcircuits. Two product assurance classes and a choice of case outlines, lead finishes, and radiation hardness assurance RHA are provided and are reflected in the complete Part or Identifying Number PIN. For this product, the requirements of MIL-M-38510 have been superseded by MIL-PRF-38535 see 6.3.

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Test

symbol

Conditions 1/ Vss  = 0 V

-55°C ≤ TC  ≤ +125°C

unless otherwise specified

Device type

Limits

Unit

Min

Max

Propagation delay time,

high-to-low level

(Kc to output)

tPHL11

VDD  = 5.0 V dc, CL  = 50 pF

RL  = 200 kO (see figures 5-15)

04

18

475

ns

54

Propagation delay time,

low-to-high level

(NOR gate)

tPLH1

04

24

640

ns

54

Propagation delay time,

low-to-high level

(OR gate)

tPLH2

04

28

750

ns

54

Propagation delay time, low-to-high level

(AND gate)

tPLH3

04

25

655

ns

54

Propagation delay time, low-to-high level

(NAND gate)

tPLH4

04

31

830

ns

54

Propagation delay time,

low-to-high level

(OR/AND gate)

tPLH5

04

24

645

ns

54

Propagation delay time,

low-to-high level

(OR/NAND gate)

t PLH6

04

26

700

ns

54

Propagation delay time, low-to-high level

(AND/NOR gate)

t PLH7

04

27

730

ns

54

Propagation delay time, low-to-high level

(AND/OR gate)

t PLH8

04

27

720

ns

54

Propagation delay time, low-to-high level

(Ka to output)

t PLH9

04

28

730

ns

54

Propagation delay time,

low-to-high level

(Kb to output)

t PLH10

04

23

605

ns

54

Propagation delay time,

low-to-high level

(Kc to output)

t PLH11

04

17

445

ns

54

Transition time, high-to-low level

tTHL

VDD  = 5.0 V dc, CL  = 50 pF RL  = 200 kO (see figure 5)

04

6

160

ns

54

Transition time, low-to-high level

tTLH

04

5

140

ns

54

Propagation delay time,

low to Z, high to Z (Kd input to output)

tPLZ, tPHZ

VDD  = 5.0 V dc, CL  = 50 pF RL  = 1.0 kO (see figure 16)

04

18

490

ns

54

Propagation delay time, Z to low, Z to high

(Kd input to output)

tPZL, tPZH

VDD  = 5.0 V dc, CL  = 50 pF RL  = 1.0 kO (see figure 16)

04

23

630

ns

54