MIL-M-38510-51 Microcircuits, Digital, Cmos, Flip-Flops And Latchets, Monolithic SiliconThis specification covers the detail requirements for monolithic silicon, CMOS, logic microcircuits. Two product assurance classes and a choice of case outlines, lead finishes, and radiation hardness assurance RHA are provided and are reflected in the complete Part or Identifying Number PIN. For this product, the requirements of MIL-M-38510 have been superseded by MIL-PRF-38535 see 6.3.

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TABLE III.  Group A inspection for device type 52 - Continued.

1/    Pins not designated may be "high" level logic, "low" level logic, or open.           8/    Test numbers 151 thru 182 shall be run in sequence and the functional

Exceptions are as follows:  VIC(pos)  tests, the VSS  terminal shall be open;                  tests shall be performed with VIH  and VDD  ≤ 5.0 V and � 18.0 V. VIC(neg)  tests, the VDD  terminal shall be open; ISS  tests, the output terminal

shall be open.                                                                                                      9/    L = VSS + 0.5 V maximum and H = VDD  - 0.5 V minimum.

2/    Test numbers 21 thru 34 shall be run in sequence.                                            10/  The maximum clock frequency (fCL) requirement is considered met if proper output state changes occur with the pulse repetition period set to that given

3/    For input voltage conditions, see figure 10.                                                                in the limits column.

4/    For input voltage conditions, see figure 11.                                                         11/  Pulse repetition period = 100 µs, 50 percent duty cycle.  The maximum clock transition time (tTLHCL) requirement is considered met if proper output state changes occur with the rise time set to that given in the limits column.

5/    Apply a clock pulse                       - - - - - - - VIH1, 2, 3

- - -  VIL1, 2, 3

12/  The minimum clock pulse width (tp) requirement is considered met if proper

6/    The device manufacturer may, at his option, measure IIL  and IIH  at                           output state changes occur with the pulse width set to that given in the

25°C for each individual input or measure all inputs together.                                   limits column.

7/    See 4.4.1c.