MIL-M-38510-51 Microcircuits, Digital, Cmos, Flip-Flops And Latchets, Monolithic SiliconThis specification covers the detail requirements for monolithic silicon, CMOS, logic microcircuits. Two product assurance classes and a choice of case outlines, lead finishes, and radiation hardness assurance RHA are provided and are reflected in the complete Part or Identifying Number PIN. For this product, the requirements of MIL-M-38510 have been superseded by MIL-PRF-38535 see 6.3.

Pages 1 - 2 - 3 - 4 - 5 - 6 - 7 - 8 - 9 - 10 - 11 - 12 - 13 - 14 - 15 - 16 - 17 - 18 - 19 - 20 - 21 - 22 - 23 - 24 - 25 - 26 - 27 - 28 - 29 - 30 - 31 - 32 - 33 - 34 - 35 - 36 - 37 - 38 - 39 - 40 - 41 - 42 - 43 - 44 - 45 - 46 - 47 - 48 - 49 - 50 - 51 - 52 - 53 - 54 - 55 - 56 - 57 - 58 - 59 - 60 - 61

TABLE III.  Group A inspection for device type 01 - Continued.

A                                  A                                    A

1/    Pins not designated may be "high" level logic, "low" level logic, or open.  Exceptions are as follows:  VIC(pos)  tests, the VSS  terminal shall be open; VIC(neg)  tests, the VDD  terminal shall be open; ISS tests, the output terminals shall be open.

2/    Test numbers 17 thru 38 shall be run in sequence.

3/    IOH  = -0.25 mA at 25°C, -0.175 mA at 125°C, -0.31 mA at -55°C.

4/    VIH1  = 3.8 V at 25°C, 3.6 V at 125°C, 3.95 V at -55°C.

5/    VIH2  = 9.5 V at 25°C, 9.25 V at 125°C, 9.75 V at -55°C.

6/    IOL = 0.5 mA at 25°C, 0.35 mA at 125°C, 0.65 mA at -55°C.

7/    VIL1 = 1.1 V at 25°C, 0.85 V at 125°C, 1.35 V at -55°C.

8/    VIL2 = 2.8 V at 25°C, 2.55 V at 125°C, 3.0 V at -55°C.

9/    For input conditions, see figure 4.

10/  For input voltage conditions, see figure 5.

11/  The device manufacturer may, at his option, measure IIL  and IIH  at 25°C for each individual input or measure all inputs together.

12/  See 4.4.1c.

13/  Test numbers 101 thru 118 shall be run in sequence and the functional tests shall be performed with VIH  and VDD  ≤ 5.0 V and � 15.0 V.

14/  L = VSS + 0.5 V maximum and H = VDD  - 0.5 V minimum.

15/  The maximum clock frequency (fCL) requirement is considered met if proper output state changes occur with the pulse repetition period set to that given in the limits column.

16/  Pulse repetition period = 100 µs, 50 percent duty cycle.  The maximum clock transition time (tTLHCL) requirement is considered met if proper output state changes occur with the rise time set to that given in the limits column.

17/  The minimum clock pulse width (tp) requirement is considered met if proper output state changes occur with the pulse width set to that given in the limits column.