MIL-M-38510-51 Microcircuits, Digital, Cmos, Flip-Flops And Latchets, Monolithic SiliconThis specification covers the detail requirements for monolithic silicon, CMOS, logic microcircuits. Two product assurance classes and a choice of case outlines, lead finishes, and radiation hardness assurance RHA are provided and are reflected in the complete Part or Identifying Number PIN. For this product, the requirements of MIL-M-38510 have been superseded by MIL-PRF-38535 see 6.3.

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MIL-M-38510/51F

TABLE I. Electrical performance characteristics - Continued.

Test	Symbol	Conditions 1/ VSS = 0 V -55°C ≤ TA ≤ +125°C Unless otherwise specified	Device type	Limits		Unit
				Min	Max
Propagation delay high to low level (Set or reset)	tPHL (R) or (S)	VDD = 5.0 V dc, CL = 50 pF	01	13	825	ns
			02	13	900
			03	10	370
			51	13	825
			52	13	900
			53	10	370
Propagation delay low to high level (Set or reset)	tPLH (R) or (S)	VDD = 5.0 V dc, CL = 50 pF	01	13	630	ns
			02	13	600
			03	10	245
			51	13	630
			52	13	600
			53	10	245
Transition time high to low levels	tTHL	VDD = 5.0 V dc, CL = 50 pF	01	10	450	ns
			02	10	490
			03	10	245
			51	10	450
			52	10	490
			53	10	245
Transition time low to high levels	tTLH	VDD = 5.0 V dc, CL = 50 pF	01	10	525	ns
			02	10	490
			03	10	360
			51	10	525
			52	10	490
			53	10	360
Maximum clock frequency	fCL(max)	VDD = 5.0 V dc, CL = 50 pF	01		1	MHz
			02		700	KHz
			51		1	MHz
			52		700	KHz
Maximum clock transition times	tTLHCL	VDD = 5.0 V dc CL = 50 pF	01		10	µs
			02
			51
			52
Minimum clock pulse width	tp	VDD = 5.0 V dc CL = 50 pF	01	300		ns
			02
			51
			52
Set-up times	tSHL, tSLH	VDD = 5.0 V dc CL = 50 pF	01	225		ns
			02
			51
			52
Hold times	tHLH, tHHL	VDD = 5.0 V dc CL = 50 pF	01	225		ns
			02
			51
			52
0utput enable time	tPZH, tPZL	VDD = 5.0 V dc CL = 50 pF	03		340	ns
			53		240
0utput disable time	tPHZ, tPLZ	VDD = 5.0 V dc CL = 50 pF	03		340	ns
			53		240

1/ Complete terminal conditions shall be a specified in table III.

2/ Input current at one input node.