11 Pins not designated may be high-level logic, low-level logic, or open. Exceptions are as follows:
a. VIC(POS) tests, the VSS terminal shall be open. b. VIC(NEG) tests, the VDD terminal shall be open. c. ISS tests, the output terminal shall be open.
21 The device manufacturer may, at his option, measure IIL and IIH at 25°C for each individual input or measure all inputs together.
31 See 4.4.1c for Ci measurement.
41 Procedures for input1output tests of the device parameters specified below are described in figures 4, 5, 6, and 7. Included with the specified parameters are test conditions and test limits at three temperatures. These tests shall be performed at each specified VDD voltage at the specified conditions. VIL1VIH test maybe performed as final attributes data.
Symbol |
Parameter |
VDD (V dc) |
Conditions |
Limits |
Unit |
|||||
TC = -55°C |
TC = 25°C |
TC = 125°C |
||||||||
Min |
Max |
Min |
Max |
Min |
Max |
|||||
VOL |
Low-level output voltage |
15 |
VI = VSS or VDD |IO| ≤ 1 µA |
0.05 |
0.05 |
0.05 |
V |
|||
VOH |
High-level output voltage |
15 |
VI = VSS or VDD |IO| ≤ 1 µA |
14.95 |
14.95 |
14.95 |
V |
|||
VIL |
Input low voltage |
5 10 15 |
VO = 0.5 V or 4.5 V VO = 1.0 V or 9.0 V VO = 1.5 V or 13.5 V |IO| ≤ 1 µA |
1.5 3.0 4.0 |
1.5 3.0 4.0 |
1.5 3.0 4.0 |
V |
|||
VIH |
Input high voltage |
5 10 15 |
VO = 0.5 V or 4.5 V VO = 1.0 V or 9.0 V VO = 1.5 V or 13.5 V |IO| ≤ 1 µA |
3.5 7.0 11.0 |
3.5 7.0 11.0 |
3.5 7.0 11.0 |
V |
|||
IOL |
Output low (sink) current |
5 15 |
VO = 0.4 V, VI = 0 or 5 V VO = 1.5 V, VI = 0 or 15 V |
0.64 4.2 |
0.51 3.4 |
0.36 2.4 |
mA |
|||
IOH |
Output high (source) current |
5 15 |
VO = 4.6 V, VI = 0 or 5 V VO = 13.5 V, VI = 0 or 15 V |
-0.64 -4.2 |
-0.51 -3.4 |
-0.36 -2.4 |
mA |
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