MIL-M-38510/56G
NOTES:
1. All outputs shall be checked for proper operation as specified in table III.
2. To step counter through its sequence, momentarily place SW2 in position 2, then with SW3 in the required logic position, toggle SW1 to increment counter.
3. See figure 2 for logic diagram and functional waveform.
4. Test requirements are considered met if: (a) counter advances with SW3 is in positions 1 and 3; (b) all counter outputs are logic "L" with SW3 in position 2; and (c) all counter outputs are logic "H" with SW3 in position 4.
5. Test requirements are considered met if, with SW3 in position 1, the counter advances to a full count during 5 clock periods with outputs achieving logic "H". At this point, SW3 is changed to position 2 and
after 5 more clock periods, a full count shall be registered with outputs achieving logic "L".
FIGURE 7. Test procedures and test circuits for JAM, PRESET ENABLE, and DATA input voltage tests.
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